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@@ -16,48 +16,19 @@
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#define ACC_IRQ_STATUS 0x12
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#define ACC_BM0_CMD 0x20
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#define ACC_BM1_CMD 0x28
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-#define ACC_BM2_CMD 0x30
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-#define ACC_BM3_CMD 0x38
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-#define ACC_BM4_CMD 0x40
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-#define ACC_BM5_CMD 0x48
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-#define ACC_BM6_CMD 0x50
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-#define ACC_BM7_CMD 0x58
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#define ACC_BM0_PRD 0x24
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#define ACC_BM1_PRD 0x2C
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-#define ACC_BM2_PRD 0x34
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-#define ACC_BM3_PRD 0x3C
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-#define ACC_BM4_PRD 0x44
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-#define ACC_BM5_PRD 0x4C
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-#define ACC_BM6_PRD 0x54
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-#define ACC_BM7_PRD 0x5C
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#define ACC_BM0_STATUS 0x21
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#define ACC_BM1_STATUS 0x29
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-#define ACC_BM2_STATUS 0x31
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-#define ACC_BM3_STATUS 0x39
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-#define ACC_BM4_STATUS 0x41
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-#define ACC_BM5_STATUS 0x49
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-#define ACC_BM6_STATUS 0x51
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-#define ACC_BM7_STATUS 0x59
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#define ACC_BM0_PNTR 0x60
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#define ACC_BM1_PNTR 0x64
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-#define ACC_BM2_PNTR 0x68
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-#define ACC_BM3_PNTR 0x6C
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-#define ACC_BM4_PNTR 0x70
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-#define ACC_BM5_PNTR 0x74
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-#define ACC_BM6_PNTR 0x78
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-#define ACC_BM7_PNTR 0x7C
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+
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/* acc_codec bar0 reg bits */
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/* ACC_IRQ_STATUS */
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#define IRQ_STS 0
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#define WU_IRQ_STS 1
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#define BM0_IRQ_STS 2
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#define BM1_IRQ_STS 3
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-#define BM2_IRQ_STS 4
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-#define BM3_IRQ_STS 5
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-#define BM4_IRQ_STS 6
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-#define BM5_IRQ_STS 7
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-#define BM6_IRQ_STS 8
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-#define BM7_IRQ_STS 9
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/* ACC_BMX_STATUS */
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#define EOP (1<<0)
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#define BM_EOP_ERR (1<<1)
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