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@@ -713,7 +713,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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* DIG1/2 can drive UNIPHY0/1/2 link A or link B
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*
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* DCE 4.0
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- * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
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+ * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
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* Supports up to 6 digital outputs
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* - 6 DIG encoder blocks.
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* - DIG to PHY mapping is hardcoded
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@@ -724,6 +724,12 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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* DIG5 drives UNIPHY2 link A, A+B
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* DIG6 drives UNIPHY2 link B
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*
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+ * DCE 4.1
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+ * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
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+ * Supports up to 6 digital outputs
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+ * - 2 DIG encoder blocks.
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+ * DIG1/2 can drive UNIPHY0/1/2 link A or link B
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+ *
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* Routing
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* crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
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* Examples:
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@@ -904,9 +910,15 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
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else
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args.v3.ucLaneNum = 4;
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- if (dig->linkb) {
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- args.v3.acConfig.ucLinkSel = 1;
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- args.v3.acConfig.ucEncoderSel = 1;
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+ if (ASIC_IS_DCE41(rdev)) {
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+ args.v3.acConfig.ucEncoderSel = dig->dig_encoder;
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+ if (dig->linkb)
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+ args.v3.acConfig.ucLinkSel = 1;
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+ } else {
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+ if (dig->linkb) {
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+ args.v3.acConfig.ucLinkSel = 1;
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+ args.v3.acConfig.ucEncoderSel = 1;
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+ }
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}
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/* Select the PLL for the PHY
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@@ -1483,6 +1495,11 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
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struct radeon_encoder_atom_dig *dig;
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uint32_t dig_enc_in_use = 0;
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+ /* on DCE41 and encoder can driver any phy so just crtc id */
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+ if (ASIC_IS_DCE41(rdev)) {
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+ return radeon_crtc->crtc_id;
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+ }
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+
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if (ASIC_IS_DCE4(rdev)) {
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dig = radeon_encoder->enc_priv;
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switch (radeon_encoder->encoder_id) {
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