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@@ -126,40 +126,43 @@ static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
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return val;
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}
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+#define pr_reg(text, ...) \
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+ printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
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+
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/* dump current cir register contents */
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static void cir_dump_regs(struct nvt_dev *nvt)
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{
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nvt_efm_enable(nvt);
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
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- printk("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
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- printk(" * CR CIR ACTIVE : 0x%x\n",
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+ pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
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+ pr_reg(" * CR CIR ACTIVE : 0x%x\n",
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nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
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- printk(" * CR CIR BASE ADDR: 0x%x\n",
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+ pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
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(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
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nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
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- printk(" * CR CIR IRQ NUM: 0x%x\n",
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+ pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
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nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
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nvt_efm_disable(nvt);
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- printk("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
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- printk(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
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- printk(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
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- printk(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
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- printk(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
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- printk(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
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- printk(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
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- printk(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
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- printk(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
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- printk(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
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- printk(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
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- printk(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
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- printk(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
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- printk(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
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- printk(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
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- printk(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
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- printk(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
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+ pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
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+ pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
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+ pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
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+ pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
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+ pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
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+ pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
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+ pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
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+ pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
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+ pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
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+ pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
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+ pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
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+ pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
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+ pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
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+ pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
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+ pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
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+ pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
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+ pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
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}
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/* dump current cir wake register contents */
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@@ -170,59 +173,59 @@ static void cir_wake_dump_regs(struct nvt_dev *nvt)
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nvt_efm_enable(nvt);
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nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
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- printk("%s: Dump CIR WAKE logical device registers:\n",
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+ pr_reg("%s: Dump CIR WAKE logical device registers:\n",
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NVT_DRIVER_NAME);
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- printk(" * CR CIR WAKE ACTIVE : 0x%x\n",
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+ pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
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nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
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- printk(" * CR CIR WAKE BASE ADDR: 0x%x\n",
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+ pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
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(nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
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- nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
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- printk(" * CR CIR WAKE IRQ NUM: 0x%x\n",
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+ nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
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+ pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
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nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
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nvt_efm_disable(nvt);
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- printk("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
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- printk(" * IRCON: 0x%x\n",
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+ pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
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+ pr_reg(" * IRCON: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
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- printk(" * IRSTS: 0x%x\n",
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+ pr_reg(" * IRSTS: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
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- printk(" * IREN: 0x%x\n",
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+ pr_reg(" * IREN: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
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- printk(" * FIFO CMP DEEP: 0x%x\n",
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+ pr_reg(" * FIFO CMP DEEP: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
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- printk(" * FIFO CMP TOL: 0x%x\n",
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+ pr_reg(" * FIFO CMP TOL: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
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- printk(" * FIFO COUNT: 0x%x\n",
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+ pr_reg(" * FIFO COUNT: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
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- printk(" * SLCH: 0x%x\n",
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+ pr_reg(" * SLCH: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
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- printk(" * SLCL: 0x%x\n",
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+ pr_reg(" * SLCL: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
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- printk(" * FIFOCON: 0x%x\n",
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+ pr_reg(" * FIFOCON: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
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- printk(" * SRXFSTS: 0x%x\n",
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+ pr_reg(" * SRXFSTS: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
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- printk(" * SAMPLE RX FIFO: 0x%x\n",
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+ pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
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- printk(" * WR FIFO DATA: 0x%x\n",
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+ pr_reg(" * WR FIFO DATA: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
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- printk(" * RD FIFO ONLY: 0x%x\n",
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+ pr_reg(" * RD FIFO ONLY: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
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- printk(" * RD FIFO ONLY IDX: 0x%x\n",
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+ pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
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- printk(" * FIFO IGNORE: 0x%x\n",
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+ pr_reg(" * FIFO IGNORE: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
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- printk(" * IRFSM: 0x%x\n",
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+ pr_reg(" * IRFSM: 0x%x\n",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
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fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
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- printk("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
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- printk("* Contents = ");
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+ pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
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+ pr_reg("* Contents = ");
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for (i = 0; i < fifo_len; i++)
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- printk("%02x ",
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+ printk(KERN_CONT "%02x ",
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nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
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- printk("\n");
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+ printk(KERN_CONT "\n");
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}
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/* detect hardware features */
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@@ -362,8 +365,10 @@ static void nvt_cir_regs_init(struct nvt_dev *nvt)
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* Enable TX and RX, specify carrier on = low, off = high, and set
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* sample period (currently 50us)
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*/
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- nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN | CIR_IRCON_RXINV |
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- CIR_IRCON_SAMPLE_PERIOD_SEL, CIR_IRCON);
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+ nvt_cir_reg_write(nvt,
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+ CIR_IRCON_TXEN | CIR_IRCON_RXEN |
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+ CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
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+ CIR_IRCON);
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/* clear hardware rx and tx fifos */
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nvt_clear_cir_fifo(nvt);
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@@ -425,7 +430,8 @@ static void nvt_enable_wake(struct nvt_dev *nvt)
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nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
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CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
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- CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL, CIR_WAKE_IRCON);
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+ CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
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+ CIR_WAKE_IRCON);
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nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
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nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
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}
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@@ -560,10 +566,10 @@ static void nvt_dump_rx_buf(struct nvt_dev *nvt)
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{
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int i;
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- printk("%s (len %d): ", __func__, nvt->pkts);
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+ printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
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for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
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- printk("0x%02x ", nvt->buf[i]);
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- printk("\n");
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+ printk(KERN_CONT "0x%02x ", nvt->buf[i]);
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+ printk(KERN_CONT "\n");
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}
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/*
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