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@@ -2146,6 +2146,13 @@ static inline void
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_il_release_nic_access(struct il_priv *il)
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{
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_il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ /*
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+ * In above we are reading CSR_GP_CNTRL register, what will flush any
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+ * previous writes, but still want write, which clear MAC_ACCESS_REQ
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+ * bit, be performed on PCI bus before any other writes scheduled on
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+ * different CPUs (after we drop reg_lock).
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+ */
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+ mmiowb();
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}
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static inline u32
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@@ -2179,7 +2186,6 @@ static inline u32
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_il_rd_prph(struct il_priv *il, u32 reg)
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{
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_il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
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- rmb();
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return _il_rd(il, HBUS_TARG_PRPH_RDAT);
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}
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@@ -2187,7 +2193,6 @@ static inline void
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_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
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{
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_il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
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- wmb();
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_il_wr(il, HBUS_TARG_PRPH_WDAT, val);
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}
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