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@@ -22,6 +22,7 @@
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/jiffies.h>
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#include <linux/clkdev.h>
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#include <linux/clkdev.h>
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+#include <linux/spinlock.h>
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#include <asm/clkdev.h>
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#include <asm/clkdev.h>
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#include <asm/div64.h>
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#include <asm/div64.h>
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@@ -29,6 +30,7 @@
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#include <mach/mx28.h>
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#include <mach/mx28.h>
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#include <mach/common.h>
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#include <mach/common.h>
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#include <mach/clock.h>
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#include <mach/clock.h>
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+#include <mach/digctl.h>
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#include "regs-clkctrl-mx28.h"
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#include "regs-clkctrl-mx28.h"
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@@ -43,6 +45,33 @@ static struct clk emi_clk;
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static struct clk saif0_clk;
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static struct clk saif0_clk;
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static struct clk saif1_clk;
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static struct clk saif1_clk;
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static struct clk clk32k_clk;
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static struct clk clk32k_clk;
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+static DEFINE_SPINLOCK(clkmux_lock);
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+
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+/*
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+ * HW_SAIF_CLKMUX_SEL:
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+ * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
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+ * clock pins selected for SAIF1 input clocks.
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+ * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
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+ * SAIF0 clock inputs selected for SAIF1 input clocks.
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+ * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
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+ * clocks.
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+ * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
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+ * clocks.
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+ */
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+int mxs_saif_clkmux_select(unsigned int clkmux)
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+{
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+ if (clkmux > 0x3)
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+ return -EINVAL;
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+
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+ spin_lock(&clkmux_lock);
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+ __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
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+ DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
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+ __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
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+ DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
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+ spin_unlock(&clkmux_lock);
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+
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+ return 0;
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+}
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static int _raw_clk_enable(struct clk *clk)
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static int _raw_clk_enable(struct clk *clk)
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{
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{
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