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@@ -4157,6 +4157,14 @@
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#define SPLL_PLL_FREQ_810MHz (0<<26)
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#define SPLL_PLL_FREQ_1350MHz (1<<26)
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+/* WRPLL */
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+#define WRPLL_CTL1 0x46040
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+#define WRPLL_CTL2 0x46060
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+#define WRPLL_PLL_ENABLE (1<<31)
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+#define WRPLL_PLL_SELECT_SSC (0x01<<28)
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+#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
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+#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
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+
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/* Port clock selection */
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#define PORT_CLK_SEL_A 0x46100
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#define PORT_CLK_SEL_B 0x46104
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