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@@ -621,29 +621,6 @@ static struct omap_dss_device sdp4430_lcd_device = {
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.phy.dsi = {
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.module = 0,
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},
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-
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- .clocks = {
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- .dispc = {
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- .channel = {
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- /* Logic Clock = 172.8 MHz */
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- .lck_div = 1,
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- /* Pixel Clock = 34.56 MHz */
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- .pck_div = 5,
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- .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
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- },
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- .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
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- },
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-
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- .dsi = {
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- .regn = 16, /* Fint = 2.4 MHz */
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- .regm = 180, /* DDR Clock = 216 MHz */
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- .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */
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- .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */
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-
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- .lp_clk_div = 10, /* LP Clock = 8.64 MHz */
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- .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
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- },
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- },
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.channel = OMAP_DSS_CHANNEL_LCD,
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};
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@@ -668,29 +645,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
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.module = 1,
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},
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-
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- .clocks = {
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- .dispc = {
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- .channel = {
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- /* Logic Clock = 172.8 MHz */
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- .lck_div = 1,
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- /* Pixel Clock = 34.56 MHz */
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- .pck_div = 5,
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- .lcd_clk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,
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- },
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- .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
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- },
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-
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- .dsi = {
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- .regn = 16, /* Fint = 2.4 MHz */
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- .regm = 180, /* DDR Clock = 216 MHz */
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- .regm_dispc = 5, /* PLL1_CLK1 = 172.8 MHz */
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- .regm_dsi = 5, /* PLL1_CLK2 = 172.8 MHz */
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-
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- .lp_clk_div = 10, /* LP Clock = 8.64 MHz */
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- .dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,
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- },
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- },
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.channel = OMAP_DSS_CHANNEL_LCD2,
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};
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