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@@ -37,6 +37,109 @@
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#define MAX_NOPID ((u32)~0)
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+/**
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+ * i915_get_pipe - return the the pipe associated with a given plane
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+ * @dev: DRM device
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+ * @plane: plane to look for
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+ *
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+ * The Intel Mesa & 2D drivers call the vblank routines with a plane number
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+ * rather than a pipe number, since they may not always be equal. This routine
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+ * maps the given @plane back to a pipe number.
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+ */
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+static int
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+i915_get_pipe(struct drm_device *dev, int plane)
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+{
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+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+ u32 dspcntr;
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+
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+ dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
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+
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+ return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
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+}
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+
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+/**
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+ * i915_get_plane - return the the plane associated with a given pipe
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+ * @dev: DRM device
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+ * @pipe: pipe to look for
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+ *
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+ * The Intel Mesa & 2D drivers call the vblank routines with a plane number
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+ * rather than a plane number, since they may not always be equal. This routine
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+ * maps the given @pipe back to a plane number.
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+ */
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+static int
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+i915_get_plane(struct drm_device *dev, int pipe)
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+{
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+ if (i915_get_pipe(dev, 0) == pipe)
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+ return 0;
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+ return 1;
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+}
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+
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+/**
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+ * i915_pipe_enabled - check if a pipe is enabled
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+ * @dev: DRM device
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+ * @pipe: pipe to check
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+ *
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+ * Reading certain registers when the pipe is disabled can hang the chip.
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+ * Use this routine to make sure the PLL is running and the pipe is active
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+ * before reading such registers if unsure.
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+ */
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+static int
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+i915_pipe_enabled(struct drm_device *dev, int pipe)
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+{
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+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+ unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
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+
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+ if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
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+ return 1;
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+
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+ return 0;
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+}
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+
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+/**
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+ * Emit a synchronous flip.
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+ *
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+ * This function must be called with the drawable spinlock held.
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+ */
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+static void
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+i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
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+ int plane)
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+{
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+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+ drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
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+ u16 x1, y1, x2, y2;
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+ int pf_planes = 1 << plane;
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+
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+ /* If the window is visible on the other plane, we have to flip on that
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+ * plane as well.
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+ */
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+ if (plane == 1) {
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+ x1 = sarea_priv->planeA_x;
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+ y1 = sarea_priv->planeA_y;
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+ x2 = x1 + sarea_priv->planeA_w;
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+ y2 = y1 + sarea_priv->planeA_h;
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+ } else {
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+ x1 = sarea_priv->planeB_x;
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+ y1 = sarea_priv->planeB_y;
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+ x2 = x1 + sarea_priv->planeB_w;
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+ y2 = y1 + sarea_priv->planeB_h;
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+ }
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+
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+ if (x2 > 0 && y2 > 0) {
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+ int i, num_rects = drw->num_rects;
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+ struct drm_clip_rect *rect = drw->rects;
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+
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+ for (i = 0; i < num_rects; i++)
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+ if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
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+ rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
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+ pf_planes = 0x3;
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+
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+ break;
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+ }
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+ }
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+
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+ i915_dispatch_flip(dev, pf_planes, 1);
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+}
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+
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/**
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* Emit blits for scheduled buffer swaps.
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*
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@@ -45,40 +148,59 @@
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static void i915_vblank_tasklet(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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- unsigned long irqflags;
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struct list_head *list, *tmp, hits, *hit;
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- int nhits, nrects, slice[2], upper[2], lower[2], i;
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- unsigned counter[2] = { atomic_read(&dev->vbl_received),
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- atomic_read(&dev->vbl_received2) };
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+ int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
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+ unsigned counter[2];
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struct drm_drawable_info *drw;
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drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
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- u32 cpp = dev_priv->cpp;
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+ u32 cpp = dev_priv->cpp, offsets[3];
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u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB)
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: XY_SRC_COPY_BLT_CMD;
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- u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |
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- (cpp << 23) | (1 << 24);
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+ u32 src_pitch = sarea_priv->pitch * cpp;
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+ u32 dst_pitch = sarea_priv->pitch * cpp;
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+ /* COPY rop (0xcc), map cpp to magic color depth constants */
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+ u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
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RING_LOCALS;
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+ if (sarea_priv->front_tiled) {
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+ cmd |= XY_SRC_COPY_BLT_DST_TILED;
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+ dst_pitch >>= 2;
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+ }
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+ if (sarea_priv->back_tiled) {
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+ cmd |= XY_SRC_COPY_BLT_SRC_TILED;
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+ src_pitch >>= 2;
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+ }
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+
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+ counter[0] = drm_vblank_count(dev, 0);
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+ counter[1] = drm_vblank_count(dev, 1);
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+
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DRM_DEBUG("\n");
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INIT_LIST_HEAD(&hits);
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nhits = nrects = 0;
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- spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
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+ /* No irqsave/restore necessary. This tasklet may be run in an
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+ * interrupt context or normal context, but we don't have to worry
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+ * about getting interrupted by something acquiring the lock, because
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+ * we are the interrupt context thing that acquires the lock.
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+ */
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+ spin_lock(&dev_priv->swaps_lock);
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/* Find buffer swaps scheduled for this vertical blank */
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list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
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drm_i915_vbl_swap_t *vbl_swap =
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list_entry(list, drm_i915_vbl_swap_t, head);
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+ int pipe = i915_get_pipe(dev, vbl_swap->plane);
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- if ((counter[vbl_swap->pipe] - vbl_swap->sequence) > (1<<23))
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+ if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
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continue;
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list_del(list);
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dev_priv->swaps_pending--;
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+ drm_vblank_put(dev, pipe);
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spin_unlock(&dev_priv->swaps_lock);
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spin_lock(&dev->drw_lock);
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@@ -116,33 +238,23 @@ static void i915_vblank_tasklet(struct drm_device *dev)
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spin_lock(&dev_priv->swaps_lock);
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}
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- if (nhits == 0) {
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- spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
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- return;
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- }
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-
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spin_unlock(&dev_priv->swaps_lock);
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- i915_kernel_lost_context(dev);
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-
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- BEGIN_LP_RING(6);
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-
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- OUT_RING(GFX_OP_DRAWRECT_INFO);
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- OUT_RING(0);
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- OUT_RING(0);
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- OUT_RING(sarea_priv->width | sarea_priv->height << 16);
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- OUT_RING(sarea_priv->width | sarea_priv->height << 16);
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- OUT_RING(0);
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-
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- ADVANCE_LP_RING();
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+ if (nhits == 0)
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+ return;
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- sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
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+ i915_kernel_lost_context(dev);
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upper[0] = upper[1] = 0;
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- slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
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- slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
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- lower[0] = sarea_priv->pipeA_y + slice[0];
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- lower[1] = sarea_priv->pipeB_y + slice[0];
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+ slice[0] = max(sarea_priv->planeA_h / nhits, 1);
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+ slice[1] = max(sarea_priv->planeB_h / nhits, 1);
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+ lower[0] = sarea_priv->planeA_y + slice[0];
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+ lower[1] = sarea_priv->planeB_y + slice[0];
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+
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+ offsets[0] = sarea_priv->front_offset;
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+ offsets[1] = sarea_priv->back_offset;
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+ offsets[2] = sarea_priv->third_offset;
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+ num_pages = sarea_priv->third_handle ? 3 : 2;
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spin_lock(&dev->drw_lock);
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@@ -154,6 +266,8 @@ static void i915_vblank_tasklet(struct drm_device *dev)
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for (i = 0; i++ < nhits;
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upper[0] = lower[0], lower[0] += slice[0],
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upper[1] = lower[1], lower[1] += slice[1]) {
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+ int init_drawrect = 1;
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+
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if (i == nhits)
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lower[0] = lower[1] = sarea_priv->height;
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@@ -161,7 +275,7 @@ static void i915_vblank_tasklet(struct drm_device *dev)
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drm_i915_vbl_swap_t *swap_hit =
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list_entry(hit, drm_i915_vbl_swap_t, head);
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struct drm_clip_rect *rect;
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- int num_rects, pipe;
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+ int num_rects, plane, front, back;
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unsigned short top, bottom;
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drw = drm_get_drawable_info(dev, swap_hit->drw_id);
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@@ -169,10 +283,50 @@ static void i915_vblank_tasklet(struct drm_device *dev)
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if (!drw)
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continue;
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+ plane = swap_hit->plane;
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+
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+ if (swap_hit->flip) {
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+ i915_dispatch_vsync_flip(dev, drw, plane);
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+ continue;
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+ }
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+
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+ if (init_drawrect) {
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+ int width = sarea_priv->width;
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+ int height = sarea_priv->height;
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+ if (IS_I965G(dev)) {
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+ BEGIN_LP_RING(4);
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+
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+ OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
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+ OUT_RING(0);
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+ OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
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+ OUT_RING(0);
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+
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+ ADVANCE_LP_RING();
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+ } else {
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+ BEGIN_LP_RING(6);
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+
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+ OUT_RING(GFX_OP_DRAWRECT_INFO);
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+ OUT_RING(0);
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+ OUT_RING(0);
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+ OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
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+ OUT_RING(0);
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+ OUT_RING(0);
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+
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+ ADVANCE_LP_RING();
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+ }
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+
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+ sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
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+
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+ init_drawrect = 0;
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+ }
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+
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rect = drw->rects;
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- pipe = swap_hit->pipe;
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- top = upper[pipe];
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- bottom = lower[pipe];
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+ top = upper[plane];
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+ bottom = lower[plane];
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+
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+ front = (dev_priv->sarea_priv->pf_current_page >>
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+ (2 * plane)) & 0x3;
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+ back = (front + 1) % num_pages;
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for (num_rects = drw->num_rects; num_rects--; rect++) {
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int y1 = max(rect->y1, top);
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@@ -184,20 +338,20 @@ static void i915_vblank_tasklet(struct drm_device *dev)
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BEGIN_LP_RING(8);
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OUT_RING(cmd);
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- OUT_RING(pitchropcpp);
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+ OUT_RING(ropcpp | dst_pitch);
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OUT_RING((y1 << 16) | rect->x1);
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OUT_RING((y2 << 16) | rect->x2);
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- OUT_RING(sarea_priv->front_offset);
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+ OUT_RING(offsets[front]);
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OUT_RING((y1 << 16) | rect->x1);
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- OUT_RING(pitchropcpp & 0xffff);
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- OUT_RING(sarea_priv->back_offset);
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+ OUT_RING(src_pitch);
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+ OUT_RING(offsets[back]);
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ADVANCE_LP_RING();
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}
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}
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}
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- spin_unlock_irqrestore(&dev->drw_lock, irqflags);
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+ spin_unlock(&dev->drw_lock);
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list_for_each_safe(hit, tmp, &hits) {
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drm_i915_vbl_swap_t *swap_hit =
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@@ -209,67 +363,112 @@ static void i915_vblank_tasklet(struct drm_device *dev)
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}
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}
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+u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
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+{
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+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+ unsigned long high_frame;
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+ unsigned long low_frame;
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+ u32 high1, high2, low, count;
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+ int pipe;
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+
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+ pipe = i915_get_pipe(dev, plane);
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+ high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
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+ low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
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+
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+ if (!i915_pipe_enabled(dev, pipe)) {
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+ printk(KERN_ERR "trying to get vblank count for disabled "
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+ "pipe %d\n", pipe);
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+ return 0;
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+ }
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+
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+ /*
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+ * High & low register fields aren't synchronized, so make sure
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+ * we get a low value that's stable across two reads of the high
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+ * register.
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+ */
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+ do {
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+ high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
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+ PIPE_FRAME_HIGH_SHIFT);
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+ low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
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+ PIPE_FRAME_LOW_SHIFT);
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+ high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
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+ PIPE_FRAME_HIGH_SHIFT);
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+ } while (high1 != high2);
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+
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+ count = (high1 << 8) | low;
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+
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+ /* count may be reset by other driver(e.g. 2D driver),
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+ we have no way to know if it is wrapped or resetted
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+ when count is zero. do a rough guess.
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+ */
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+ if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
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+ dev->last_vblank[pipe] = 0;
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+
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+ return count;
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+}
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+
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irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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- u16 temp;
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+ u32 iir;
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u32 pipea_stats, pipeb_stats;
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-
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- pipea_stats = I915_READ(I915REG_PIPEASTAT);
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- pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
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-
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- temp = I915_READ16(I915REG_INT_IDENTITY_R);
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-
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- temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG);
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-
|
|
|
- DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
|
|
|
-
|
|
|
- if (temp == 0)
|
|
|
+ int vblank = 0;
|
|
|
+
|
|
|
+ iir = I915_READ(I915REG_INT_IDENTITY_R);
|
|
|
+ if (iir == 0) {
|
|
|
+ DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
|
|
|
+ iir,
|
|
|
+ I915_READ(I915REG_INT_MASK_R),
|
|
|
+ I915_READ(I915REG_INT_ENABLE_R),
|
|
|
+ I915_READ(I915REG_PIPEASTAT),
|
|
|
+ I915_READ(I915REG_PIPEBSTAT));
|
|
|
return IRQ_NONE;
|
|
|
+ }
|
|
|
|
|
|
- I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
|
|
|
- (void) I915_READ16(I915REG_INT_IDENTITY_R);
|
|
|
- DRM_READMEMORYBARRIER();
|
|
|
-
|
|
|
- dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
|
+ /*
|
|
|
+ * Clear the PIPE(A|B)STAT regs before the IIR otherwise
|
|
|
+ * we may get extra interrupts.
|
|
|
+ */
|
|
|
+ if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
|
|
|
+ pipea_stats = I915_READ(I915REG_PIPEASTAT);
|
|
|
+ if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
|
|
|
+ I915_VBLANK_INTERRUPT_STATUS))
|
|
|
+ {
|
|
|
+ vblank++;
|
|
|
+ drm_handle_vblank(dev, i915_get_plane(dev, 0));
|
|
|
+ }
|
|
|
+ I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
|
|
|
+ }
|
|
|
+ if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
|
|
|
+ pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
|
|
|
+ if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
|
|
|
+ I915_VBLANK_INTERRUPT_STATUS))
|
|
|
+ {
|
|
|
+ vblank++;
|
|
|
+ drm_handle_vblank(dev, i915_get_plane(dev, 1));
|
|
|
+ }
|
|
|
+ I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
|
|
|
+ }
|
|
|
|
|
|
- if (temp & USER_INT_FLAG)
|
|
|
- DRM_WAKEUP(&dev_priv->irq_queue);
|
|
|
+ if (dev_priv->sarea_priv)
|
|
|
+ dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
|
|
|
|
- if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
|
|
|
- int vblank_pipe = dev_priv->vblank_pipe;
|
|
|
-
|
|
|
- if ((vblank_pipe &
|
|
|
- (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
|
|
|
- == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
|
|
|
- if (temp & VSYNC_PIPEA_FLAG)
|
|
|
- atomic_inc(&dev->vbl_received);
|
|
|
- if (temp & VSYNC_PIPEB_FLAG)
|
|
|
- atomic_inc(&dev->vbl_received2);
|
|
|
- } else if (((temp & VSYNC_PIPEA_FLAG) &&
|
|
|
- (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
|
|
|
- ((temp & VSYNC_PIPEB_FLAG) &&
|
|
|
- (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
|
|
|
- atomic_inc(&dev->vbl_received);
|
|
|
-
|
|
|
- DRM_WAKEUP(&dev->vbl_queue);
|
|
|
- drm_vbl_send_signals(dev);
|
|
|
+ I915_WRITE(I915REG_INT_IDENTITY_R, iir);
|
|
|
+ (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */
|
|
|
|
|
|
+ if (iir & I915_USER_INTERRUPT) {
|
|
|
+ DRM_WAKEUP(&dev_priv->irq_queue);
|
|
|
+ }
|
|
|
+ if (vblank) {
|
|
|
if (dev_priv->swaps_pending > 0)
|
|
|
drm_locked_tasklet(dev, i915_vblank_tasklet);
|
|
|
- I915_WRITE(I915REG_PIPEASTAT,
|
|
|
- pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
|
|
|
- I915_VBLANK_CLEAR);
|
|
|
- I915_WRITE(I915REG_PIPEBSTAT,
|
|
|
- pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
|
|
|
- I915_VBLANK_CLEAR);
|
|
|
}
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
}
|
|
|
|
|
|
-static int i915_emit_irq(struct drm_device * dev)
|
|
|
+static int i915_emit_irq(struct drm_device *dev)
|
|
|
{
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
RING_LOCALS;
|
|
@@ -316,42 +515,12 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
|
|
|
READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
|
|
|
}
|
|
|
|
|
|
- dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
-static int i915_driver_vblank_do_wait(struct drm_device *dev, unsigned int *sequence,
|
|
|
- atomic_t *counter)
|
|
|
-{
|
|
|
- drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
- unsigned int cur_vblank;
|
|
|
- int ret = 0;
|
|
|
-
|
|
|
- if (!dev_priv) {
|
|
|
- DRM_ERROR("called with no initialization\n");
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
-
|
|
|
- DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
|
|
|
- (((cur_vblank = atomic_read(counter))
|
|
|
- - *sequence) <= (1<<23)));
|
|
|
-
|
|
|
- *sequence = cur_vblank;
|
|
|
-
|
|
|
+ if (dev_priv->sarea_priv)
|
|
|
+ dev_priv->sarea_priv->last_dispatch =
|
|
|
+ READ_BREADCRUMB(dev_priv);
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-
|
|
|
-int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
|
|
|
-{
|
|
|
- return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
|
|
|
-}
|
|
|
-
|
|
|
-int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
|
|
|
-{
|
|
|
- return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
|
|
|
-}
|
|
|
-
|
|
|
/* Needs the lock as it touches the ring.
|
|
|
*/
|
|
|
int i915_irq_emit(struct drm_device *dev, void *data,
|
|
@@ -394,18 +563,96 @@ int i915_irq_wait(struct drm_device *dev, void *data,
|
|
|
return i915_wait_irq(dev, irqwait->irq_seq);
|
|
|
}
|
|
|
|
|
|
+int i915_enable_vblank(struct drm_device *dev, int plane)
|
|
|
+{
|
|
|
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
+ int pipe = i915_get_pipe(dev, plane);
|
|
|
+ u32 pipestat_reg = 0;
|
|
|
+ u32 pipestat;
|
|
|
+
|
|
|
+ switch (pipe) {
|
|
|
+ case 0:
|
|
|
+ pipestat_reg = I915REG_PIPEASTAT;
|
|
|
+ dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
|
|
|
+ break;
|
|
|
+ case 1:
|
|
|
+ pipestat_reg = I915REG_PIPEBSTAT;
|
|
|
+ dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
|
|
|
+ pipe);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (pipestat_reg)
|
|
|
+ {
|
|
|
+ pipestat = I915_READ (pipestat_reg);
|
|
|
+ /*
|
|
|
+ * Older chips didn't have the start vblank interrupt,
|
|
|
+ * but
|
|
|
+ */
|
|
|
+ if (IS_I965G (dev))
|
|
|
+ pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
|
|
|
+ else
|
|
|
+ pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
|
|
|
+ /*
|
|
|
+ * Clear any pending status
|
|
|
+ */
|
|
|
+ pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
|
|
|
+ I915_VBLANK_INTERRUPT_STATUS);
|
|
|
+ I915_WRITE(pipestat_reg, pipestat);
|
|
|
+ }
|
|
|
+ I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void i915_disable_vblank(struct drm_device *dev, int plane)
|
|
|
+{
|
|
|
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
+ int pipe = i915_get_pipe(dev, plane);
|
|
|
+ u32 pipestat_reg = 0;
|
|
|
+ u32 pipestat;
|
|
|
+
|
|
|
+ switch (pipe) {
|
|
|
+ case 0:
|
|
|
+ pipestat_reg = I915REG_PIPEASTAT;
|
|
|
+ dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
|
|
|
+ break;
|
|
|
+ case 1:
|
|
|
+ pipestat_reg = I915REG_PIPEBSTAT;
|
|
|
+ dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
|
|
|
+ pipe);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
|
|
|
+ if (pipestat_reg)
|
|
|
+ {
|
|
|
+ pipestat = I915_READ (pipestat_reg);
|
|
|
+ pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
|
|
|
+ I915_VBLANK_INTERRUPT_ENABLE);
|
|
|
+ /*
|
|
|
+ * Clear any pending status
|
|
|
+ */
|
|
|
+ pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
|
|
|
+ I915_VBLANK_INTERRUPT_STATUS);
|
|
|
+ I915_WRITE(pipestat_reg, pipestat);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
static void i915_enable_interrupt (struct drm_device *dev)
|
|
|
{
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
- u16 flag;
|
|
|
|
|
|
- flag = 0;
|
|
|
- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
|
|
|
- flag |= VSYNC_PIPEA_FLAG;
|
|
|
- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
|
|
|
- flag |= VSYNC_PIPEB_FLAG;
|
|
|
+ dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
|
|
|
|
|
|
- I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag);
|
|
|
+ I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
|
|
|
+ dev_priv->irq_enabled = 1;
|
|
|
}
|
|
|
|
|
|
/* Set the vblank monitor pipe
|
|
@@ -428,8 +675,6 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
|
|
|
|
|
|
dev_priv->vblank_pipe = pipe->pipe;
|
|
|
|
|
|
- i915_enable_interrupt (dev);
|
|
|
-
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
@@ -447,9 +692,9 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
|
|
|
|
|
|
flag = I915_READ(I915REG_INT_ENABLE_R);
|
|
|
pipe->pipe = 0;
|
|
|
- if (flag & VSYNC_PIPEA_FLAG)
|
|
|
+ if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
|
|
|
pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
|
|
|
- if (flag & VSYNC_PIPEB_FLAG)
|
|
|
+ if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
|
|
|
pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
|
|
|
|
|
|
return 0;
|
|
@@ -464,27 +709,30 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
drm_i915_vblank_swap_t *swap = data;
|
|
|
drm_i915_vbl_swap_t *vbl_swap;
|
|
|
- unsigned int pipe, seqtype, curseq;
|
|
|
+ unsigned int pipe, seqtype, curseq, plane;
|
|
|
unsigned long irqflags;
|
|
|
struct list_head *list;
|
|
|
+ int ret;
|
|
|
|
|
|
if (!dev_priv) {
|
|
|
DRM_ERROR("%s called with no initialization\n", __func__);
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
|
|
|
- if (dev_priv->sarea_priv->rotation) {
|
|
|
+ if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {
|
|
|
DRM_DEBUG("Rotation not supported\n");
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
|
|
|
if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
|
|
|
- _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) {
|
|
|
+ _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
|
|
|
+ _DRM_VBLANK_FLIP)) {
|
|
|
DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
|
|
|
- pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
|
|
|
+ plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
|
|
|
+ pipe = i915_get_pipe(dev, plane);
|
|
|
|
|
|
seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
|
|
|
|
|
@@ -495,6 +743,11 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
|
|
|
|
spin_lock_irqsave(&dev->drw_lock, irqflags);
|
|
|
|
|
|
+ /* It makes no sense to schedule a swap for a drawable that doesn't have
|
|
|
+ * valid information at this point. E.g. this could mean that the X
|
|
|
+ * server is too old to push drawable information to the DRM, in which
|
|
|
+ * case all such swaps would become ineffective.
|
|
|
+ */
|
|
|
if (!drm_get_drawable_info(dev, swap->drawable)) {
|
|
|
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
|
|
DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
|
|
@@ -503,7 +756,8 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
|
|
|
|
|
- curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received);
|
|
|
+ drm_update_vblank_count(dev, pipe);
|
|
|
+ curseq = drm_vblank_count(dev, pipe);
|
|
|
|
|
|
if (seqtype == _DRM_VBLANK_RELATIVE)
|
|
|
swap->sequence += curseq;
|
|
@@ -517,14 +771,43 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
|
}
|
|
|
}
|
|
|
|
|
|
+ if (swap->seqtype & _DRM_VBLANK_FLIP) {
|
|
|
+ swap->sequence--;
|
|
|
+
|
|
|
+ if ((curseq - swap->sequence) <= (1<<23)) {
|
|
|
+ struct drm_drawable_info *drw;
|
|
|
+
|
|
|
+ LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
+
|
|
|
+ spin_lock_irqsave(&dev->drw_lock, irqflags);
|
|
|
+
|
|
|
+ drw = drm_get_drawable_info(dev, swap->drawable);
|
|
|
+
|
|
|
+ if (!drw) {
|
|
|
+ spin_unlock_irqrestore(&dev->drw_lock,
|
|
|
+ irqflags);
|
|
|
+ DRM_DEBUG("Invalid drawable ID %d\n",
|
|
|
+ swap->drawable);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ i915_dispatch_vsync_flip(dev, drw, plane);
|
|
|
+
|
|
|
+ spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
|
|
|
|
|
|
list_for_each(list, &dev_priv->vbl_swaps.head) {
|
|
|
vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
|
|
|
|
|
|
if (vbl_swap->drw_id == swap->drawable &&
|
|
|
- vbl_swap->pipe == pipe &&
|
|
|
+ vbl_swap->plane == plane &&
|
|
|
vbl_swap->sequence == swap->sequence) {
|
|
|
+ vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
|
|
|
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
|
|
|
DRM_DEBUG("Already scheduled\n");
|
|
|
return 0;
|
|
@@ -547,9 +830,19 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
|
|
|
|
|
|
DRM_DEBUG("\n");
|
|
|
|
|
|
+ ret = drm_vblank_get(dev, pipe);
|
|
|
+ if (ret) {
|
|
|
+ drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
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vbl_swap->drw_id = swap->drawable;
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- vbl_swap->pipe = pipe;
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+ vbl_swap->plane = plane;
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vbl_swap->sequence = swap->sequence;
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+ vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
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+
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+ if (vbl_swap->flip)
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+ swap->sequence++;
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spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
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|
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|
@@ -567,37 +860,57 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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- I915_WRITE16(I915REG_HWSTAM, 0xfffe);
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+ I915_WRITE16(I915REG_HWSTAM, 0xeffe);
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I915_WRITE16(I915REG_INT_MASK_R, 0x0);
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I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
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}
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|
-void i915_driver_irq_postinstall(struct drm_device * dev)
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+int i915_driver_irq_postinstall(struct drm_device * dev)
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|
|
{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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+ int ret, num_pipes = 2;
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|
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|
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spin_lock_init(&dev_priv->swaps_lock);
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INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
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dev_priv->swaps_pending = 0;
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|
|
- if (!dev_priv->vblank_pipe)
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|
- dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
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|
|
+ dev_priv->user_irq_refcount = 0;
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|
+ dev_priv->irq_enable_reg = 0;
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|
+
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|
+ ret = drm_vblank_init(dev, num_pipes);
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|
|
+ if (ret)
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|
+ return ret;
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|
+
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|
|
+ dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
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+
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|
|
i915_enable_interrupt(dev);
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|
|
DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
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|
+
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|
|
+ /*
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|
|
+ * Initialize the hardware status page IRQ location.
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|
+ */
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+
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|
|
+ I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
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|
|
+ return 0;
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|
|
}
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|
|
|
|
|
void i915_driver_irq_uninstall(struct drm_device * dev)
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|
|
{
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|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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|
|
- u16 temp;
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|
|
+ u32 temp;
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|
|
|
|
|
if (!dev_priv)
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|
|
return;
|
|
|
|
|
|
- I915_WRITE16(I915REG_HWSTAM, 0xffff);
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|
|
- I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
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|
|
- I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
|
|
|
-
|
|
|
- temp = I915_READ16(I915REG_INT_IDENTITY_R);
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|
|
- I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
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|
|
+ dev_priv->irq_enabled = 0;
|
|
|
+ I915_WRITE(I915REG_HWSTAM, 0xffffffff);
|
|
|
+ I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
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|
|
+ I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
|
|
|
+
|
|
|
+ temp = I915_READ(I915REG_PIPEASTAT);
|
|
|
+ I915_WRITE(I915REG_PIPEASTAT, temp);
|
|
|
+ temp = I915_READ(I915REG_PIPEBSTAT);
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|
|
+ I915_WRITE(I915REG_PIPEBSTAT, temp);
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|
|
+ temp = I915_READ(I915REG_INT_IDENTITY_R);
|
|
|
+ I915_WRITE(I915REG_INT_IDENTITY_R, temp);
|
|
|
}
|