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@@ -8108,8 +8108,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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/* Program the jumbo buffer descriptor ring control
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/* Program the jumbo buffer descriptor ring control
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* blocks on those devices that have them.
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* blocks on those devices that have them.
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*/
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*/
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- if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
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- !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
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+ if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
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+ ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
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+ !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) {
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/* Setup replenish threshold. */
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/* Setup replenish threshold. */
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tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
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tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
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@@ -13329,7 +13330,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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}
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}
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/* Determine TSO capabilities */
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/* Determine TSO capabilities */
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- if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
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+ if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
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+ ; /* Do nothing. HW bug. */
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+ else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
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tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
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else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
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else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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@@ -13380,7 +13383,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
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tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
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}
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}
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- if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
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+ if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
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+ tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
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tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
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tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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