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@@ -15,7 +15,6 @@
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#include <linux/oprofile.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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-#include <linux/percpu.h>
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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@@ -24,10 +23,8 @@
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#include "op_x86_model.h"
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#include "op_counter.h"
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-#define NUM_COUNTERS 32
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-#define NUM_HARDWARE_COUNTERS 4
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-#define NUM_CONTROLS 32
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-#define NUM_HARDWARE_CONTROLS 4
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+#define NUM_COUNTERS 4
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+#define NUM_CONTROLS 4
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#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
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#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
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@@ -51,7 +48,6 @@
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#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
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static unsigned long reset_value[NUM_COUNTERS];
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-DECLARE_PER_CPU(int, switch_index);
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#ifdef CONFIG_OPROFILE_IBS
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@@ -134,17 +130,15 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
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int i;
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for (i = 0; i < NUM_COUNTERS; i++) {
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- int hw_counter = i % NUM_HARDWARE_COUNTERS;
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- if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + hw_counter))
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- msrs->counters[i].addr = MSR_K7_PERFCTR0 + hw_counter;
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+ if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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+ msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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else
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msrs->counters[i].addr = 0;
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}
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for (i = 0; i < NUM_CONTROLS; i++) {
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- int hw_control = i % NUM_HARDWARE_CONTROLS;
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- if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + hw_control))
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- msrs->controls[i].addr = MSR_K7_EVNTSEL0 + hw_control;
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+ if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
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+ msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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else
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msrs->controls[i].addr = 0;
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}
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@@ -156,16 +150,8 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
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unsigned int low, high;
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int i;
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- for (i = 0; i < NUM_HARDWARE_CONTROLS; ++i) {
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- int offset = i + __get_cpu_var(switch_index);
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- if (counter_config[offset].enabled)
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- reset_value[offset] = counter_config[offset].count;
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- else
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- reset_value[offset] = 0;
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- }
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-
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/* clear all counters */
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- for (i = 0 ; i < NUM_HARDWARE_CONTROLS; ++i) {
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+ for (i = 0 ; i < NUM_CONTROLS; ++i) {
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if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
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continue;
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CTRL_READ(low, high, msrs, i);
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@@ -175,31 +161,34 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
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}
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/* avoid a false detection of ctr overflows in NMI handler */
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- for (i = 0; i < NUM_HARDWARE_COUNTERS; ++i) {
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+ for (i = 0; i < NUM_COUNTERS; ++i) {
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if (unlikely(!CTR_IS_RESERVED(msrs, i)))
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continue;
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CTR_WRITE(1, msrs, i);
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}
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/* enable active counters */
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- for (i = 0; i < NUM_HARDWARE_COUNTERS; ++i) {
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- int offset = i + __get_cpu_var(switch_index);
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- if ((counter_config[offset].enabled) && (CTR_IS_RESERVED(msrs, i))) {
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- CTR_WRITE(counter_config[offset].count, msrs, i);
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+ for (i = 0; i < NUM_COUNTERS; ++i) {
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+ if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
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+ reset_value[i] = counter_config[i].count;
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+
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+ CTR_WRITE(counter_config[i].count, msrs, i);
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CTRL_READ(low, high, msrs, i);
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CTRL_CLEAR_LO(low);
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CTRL_CLEAR_HI(high);
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CTRL_SET_ENABLE(low);
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- CTRL_SET_USR(low, counter_config[offset].user);
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- CTRL_SET_KERN(low, counter_config[offset].kernel);
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- CTRL_SET_UM(low, counter_config[offset].unit_mask);
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- CTRL_SET_EVENT_LOW(low, counter_config[offset].event);
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- CTRL_SET_EVENT_HIGH(high, counter_config[offset].event);
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+ CTRL_SET_USR(low, counter_config[i].user);
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+ CTRL_SET_KERN(low, counter_config[i].kernel);
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+ CTRL_SET_UM(low, counter_config[i].unit_mask);
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+ CTRL_SET_EVENT_LOW(low, counter_config[i].event);
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+ CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
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CTRL_SET_HOST_ONLY(high, 0);
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CTRL_SET_GUEST_ONLY(high, 0);
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CTRL_WRITE(low, high, msrs, i);
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+ } else {
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+ reset_value[i] = 0;
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}
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}
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}
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@@ -287,14 +276,13 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
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unsigned int low, high;
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int i;
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- for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) {
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- int offset = i + __get_cpu_var(switch_index);
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- if (!reset_value[offset])
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+ for (i = 0 ; i < NUM_COUNTERS; ++i) {
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+ if (!reset_value[i])
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continue;
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CTR_READ(low, high, msrs, i);
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if (CTR_OVERFLOWED(low)) {
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- oprofile_add_sample(regs, offset);
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- CTR_WRITE(reset_value[offset], msrs, i);
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+ oprofile_add_sample(regs, i);
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+ CTR_WRITE(reset_value[i], msrs, i);
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}
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}
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@@ -310,10 +298,8 @@ static void op_amd_start(struct op_msrs const * const msrs)
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{
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unsigned int low, high;
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int i;
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-
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- for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) {
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- int offset = i + __get_cpu_var(switch_index);
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- if (reset_value[offset]) {
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+ for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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+ if (reset_value[i]) {
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CTRL_READ(low, high, msrs, i);
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CTRL_SET_ACTIVE(low);
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CTRL_WRITE(low, high, msrs, i);
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@@ -343,8 +329,8 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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/* Subtle: stop on all counters to avoid race with
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* setting our pm callback */
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- for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) {
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- if (!reset_value[i + per_cpu(switch_index, smp_processor_id())])
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+ for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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+ if (!reset_value[i])
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continue;
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CTRL_READ(low, high, msrs, i);
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CTRL_SET_INACTIVE(low);
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@@ -370,11 +356,11 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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- for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) {
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+ for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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if (CTR_IS_RESERVED(msrs, i))
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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}
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- for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) {
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+ for (i = 0 ; i < NUM_CONTROLS ; ++i) {
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if (CTRL_IS_RESERVED(msrs, i))
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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@@ -548,8 +534,6 @@ struct op_x86_model_spec const op_amd_spec = {
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.exit = op_amd_exit,
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.num_counters = NUM_COUNTERS,
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.num_controls = NUM_CONTROLS,
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- .num_hardware_counters = NUM_HARDWARE_COUNTERS,
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- .num_hardware_controls = NUM_HARDWARE_CONTROLS,
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.fill_in_addresses = &op_amd_fill_in_addresses,
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.setup_ctrs = &op_amd_setup_ctrs,
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.check_ctrs = &op_amd_check_ctrs,
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