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@@ -190,7 +190,7 @@ static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
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static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
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-static void ahci_phy_reset(struct ata_port *ap);
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+static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
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static void ahci_irq_clear(struct ata_port *ap);
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static void ahci_eng_timeout(struct ata_port *ap);
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static int ahci_port_start(struct ata_port *ap);
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@@ -230,7 +230,7 @@ static const struct ata_port_operations ahci_ops = {
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.tf_read = ahci_tf_read,
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- .phy_reset = ahci_phy_reset,
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+ .probe_reset = ahci_probe_reset,
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.qc_prep = ahci_qc_prep,
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.qc_issue = ahci_qc_issue,
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@@ -252,8 +252,7 @@ static const struct ata_port_info ahci_port_info[] = {
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{
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.sht = &ahci_sht,
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.host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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- ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
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- ATA_FLAG_PIO_DMA,
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+ ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
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.pio_mask = 0x1f, /* pio0-4 */
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &ahci_ops,
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@@ -515,28 +514,35 @@ static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
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pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
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}
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-static void ahci_phy_reset(struct ata_port *ap)
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+static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
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{
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- void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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- struct ata_device *dev = &ap->device[0];
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- u32 new_tmp, tmp;
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+ int rc;
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+
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+ DPRINTK("ENTER\n");
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ahci_stop_engine(ap);
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- __sata_phy_reset(ap);
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+ rc = sata_std_hardreset(ap, verbose, class);
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ahci_start_engine(ap);
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- if (ap->flags & ATA_FLAG_PORT_DISABLED)
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- return;
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+ if (rc == 0)
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+ *class = ahci_dev_classify(ap);
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+ if (*class == ATA_DEV_UNKNOWN)
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+ *class = ATA_DEV_NONE;
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- dev->class = ahci_dev_classify(ap);
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- if (!ata_dev_present(dev)) {
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- ata_port_disable(ap);
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- return;
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- }
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+ DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
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+ return rc;
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+}
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+
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+static void ahci_postreset(struct ata_port *ap, unsigned int *class)
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+{
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+ void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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+ u32 new_tmp, tmp;
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+
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+ ata_std_postreset(ap, class);
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/* Make sure port's ATAPI bit is set appropriately */
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new_tmp = tmp = readl(port_mmio + PORT_CMD);
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- if (dev->class == ATA_DEV_ATAPI)
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+ if (*class == ATA_DEV_ATAPI)
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new_tmp |= PORT_CMD_ATAPI;
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else
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new_tmp &= ~PORT_CMD_ATAPI;
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@@ -546,6 +552,12 @@ static void ahci_phy_reset(struct ata_port *ap)
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}
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}
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+static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
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+{
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+ return ata_drive_probe_reset(ap, NULL, NULL, ahci_hardreset,
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+ ahci_postreset, classes);
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+}
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+
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static u8 ahci_check_status(struct ata_port *ap)
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{
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void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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