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@@ -226,7 +226,7 @@ static void sky2_power_on(struct sky2_hw *hw)
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/* disable Core Clock Division, */
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sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
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- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
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+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
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/* enable bits are inverted */
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sky2_write8(hw, B2_Y2_CLK_GATE,
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Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
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@@ -268,7 +268,7 @@ static void sky2_power_on(struct sky2_hw *hw)
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static void sky2_power_aux(struct sky2_hw *hw)
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{
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- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
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+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
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sky2_write8(hw, B2_Y2_CLK_GATE, 0);
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else
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/* enable bits are inverted */
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@@ -651,7 +651,7 @@ static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
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reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
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reg1 &= ~phy_power[port];
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- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
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+ if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
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reg1 |= coma_mode[port];
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sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
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@@ -823,7 +823,9 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
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sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
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- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
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+ if (hw->chip_id == CHIP_ID_YUKON_XL &&
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+ hw->chip_rev == CHIP_REV_YU_XL_A0 &&
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+ port == 1) {
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/* WA DEV_472 -- looks like crossed wires on port 2 */
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/* clear GMAC 1 Control reset */
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sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
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