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@@ -2344,6 +2344,26 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
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}
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}
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+/*
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+ * When we disable a pipe, we need to clear any pending scanline wait events
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+ * to avoid hanging the ring, which we assume we are waiting on.
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+ */
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+static void intel_clear_scanline_wait(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ u32 tmp;
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+
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+ if (IS_GEN2(dev))
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+ /* Can't break the hang on i8xx */
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+ return;
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+
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+ tmp = I915_READ(PRB0_CTL);
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+ if (tmp & RING_WAIT) {
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+ I915_WRITE(PRB0_CTL, tmp);
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+ POSTING_READ(PRB0_CTL);
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+ }
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+}
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+
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/**
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* Sets the power management mode of the pipe and plane.
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*/
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@@ -2366,7 +2386,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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* with multiple pipes prior to enabling to new pipe.
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*
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* When switching off the display, make sure the cursor is
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- * properly hidden prior to disabling the pipe.
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+ * properly hidden and there are no pending waits prior to
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+ * disabling the pipe.
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*/
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if (mode == DRM_MODE_DPMS_ON)
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intel_update_watermarks(dev);
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@@ -2377,8 +2398,14 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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if (mode == DRM_MODE_DPMS_ON)
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intel_crtc_update_cursor(crtc);
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- else
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+ else {
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+ /* XXX Note that this is not a complete solution, but a hack
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+ * to avoid the most frequently hit hang.
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+ */
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+ intel_clear_scanline_wait(dev);
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+
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intel_update_watermarks(dev);
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+ }
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if (!dev->primary->master)
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return;
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