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@@ -59,10 +59,10 @@ static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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- case 0x4313:
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- case 0x4331:
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- case 43224:
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- case 43225:
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+ case BCMA_CHIP_ID_BCM4313:
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+ case BCMA_CHIP_ID_BCM4331:
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+ case BCMA_CHIP_ID_BCM43224:
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+ case BCMA_CHIP_ID_BCM43225:
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break;
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default:
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pr_err("PLL init unknown for device 0x%04X\n",
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@@ -76,13 +76,13 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
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u32 min_msk = 0, max_msk = 0;
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switch (bus->chipinfo.id) {
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- case 0x4313:
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+ case BCMA_CHIP_ID_BCM4313:
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min_msk = 0x200D;
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max_msk = 0xFFFF;
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break;
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- case 0x4331:
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- case 43224:
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- case 43225:
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+ case BCMA_CHIP_ID_BCM4331:
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+ case BCMA_CHIP_ID_BCM43224:
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+ case BCMA_CHIP_ID_BCM43225:
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break;
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default:
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pr_err("PMU resource config unknown for device 0x%04X\n",
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@@ -101,10 +101,10 @@ void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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- case 0x4313:
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- case 0x4331:
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- case 43224:
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- case 43225:
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+ case BCMA_CHIP_ID_BCM4313:
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+ case BCMA_CHIP_ID_BCM4331:
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+ case BCMA_CHIP_ID_BCM43224:
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+ case BCMA_CHIP_ID_BCM43225:
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break;
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default:
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pr_err("PMU switch/regulators init unknown for device "
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@@ -138,15 +138,15 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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- case 0x4313:
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+ case BCMA_CHIP_ID_BCM4313:
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
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break;
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- case 0x4331:
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- case 43431:
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+ case BCMA_CHIP_ID_BCM4331:
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+ case BCMA_CHIP_ID_BCM43431:
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/* Ext PA lines must be enabled for tx on BCM4331 */
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bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
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break;
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- case 43224:
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+ case BCMA_CHIP_ID_BCM43224:
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if (bus->chipinfo.rev == 0) {
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pr_err("Workarounds for 43224 rev 0 not fully "
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"implemented\n");
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@@ -155,7 +155,7 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
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}
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break;
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- case 43225:
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+ case BCMA_CHIP_ID_BCM43225:
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break;
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default:
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pr_err("Workarounds unknown for device 0x%04X\n",
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@@ -194,17 +194,17 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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- case 0x4716:
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- case 0x4748:
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- case 47162:
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- case 0x4313:
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- case 0x5357:
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- case 0x4749:
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- case 53572:
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+ case BCMA_CHIP_ID_BCM4716:
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+ case BCMA_CHIP_ID_BCM4748:
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+ case BCMA_CHIP_ID_BCM47162:
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+ case BCMA_CHIP_ID_BCM4313:
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+ case BCMA_CHIP_ID_BCM5357:
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+ case BCMA_CHIP_ID_BCM4749:
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+ case BCMA_CHIP_ID_BCM53572:
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/* always 20Mhz */
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return 20000 * 1000;
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- case 0x5356:
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- case 0x5300:
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+ case BCMA_CHIP_ID_BCM5356:
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+ case BCMA_CHIP_ID_BCM4706:
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/* always 25Mhz */
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return 25000 * 1000;
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default:
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@@ -227,7 +227,8 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
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BUG_ON(!m || m > 4);
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- if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
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+ bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
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/* Detect failure in clock setting */
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tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
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if (tmp & 0x40000)
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@@ -259,22 +260,22 @@ u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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- case 0x4716:
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- case 0x4748:
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- case 47162:
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+ case BCMA_CHIP_ID_BCM4716:
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+ case BCMA_CHIP_ID_BCM4748:
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+ case BCMA_CHIP_ID_BCM47162:
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return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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- case 0x5356:
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+ case BCMA_CHIP_ID_BCM5356:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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- case 0x5357:
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- case 0x4749:
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+ case BCMA_CHIP_ID_BCM5357:
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+ case BCMA_CHIP_ID_BCM4749:
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return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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- case 0x5300:
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+ case BCMA_CHIP_ID_BCM4706:
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return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
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BCMA_CC_PMU5_MAINPLL_SSB);
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- case 53572:
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+ case BCMA_CHIP_ID_BCM53572:
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return 75000000;
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default:
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pr_warn("No backplane clock specified for %04X device, "
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@@ -289,17 +290,17 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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- if (bus->chipinfo.id == 53572)
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+ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
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return 300000000;
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if (cc->pmu.rev >= 5) {
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u32 pll;
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switch (bus->chipinfo.id) {
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- case 0x5356:
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+ case BCMA_CHIP_ID_BCM5356:
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pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
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break;
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- case 0x5357:
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- case 0x4749:
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+ case BCMA_CHIP_ID_BCM5357:
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+ case BCMA_CHIP_ID_BCM4749:
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pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
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break;
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default:
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@@ -307,7 +308,7 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
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break;
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}
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- /* TODO: if (bus->chipinfo.id == 0x5300)
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+ /* TODO: if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
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return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
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return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
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}
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