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@@ -610,7 +610,7 @@ static u8 bnx2x_bmac_enable(struct link_params *params,
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/* reset and unreset the BigMac */
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REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
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(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
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- udelay(10);
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+ msleep(1);
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REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
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(MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
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@@ -3525,13 +3525,19 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
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DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
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/* Enable CL37 BAM */
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- bnx2x_cl45_read(bp, phy,
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- MDIO_AN_DEVAD,
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- MDIO_AN_REG_8073_BAM, &val);
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- bnx2x_cl45_write(bp, phy,
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- MDIO_AN_DEVAD,
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- MDIO_AN_REG_8073_BAM, val | 1);
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+ if (REG_RD(bp, params->shmem_base +
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+ offsetof(struct shmem_region, dev_info.
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+ port_hw_config[params->port].default_cfg)) &
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+ PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
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+ bnx2x_cl45_read(bp, phy,
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+ MDIO_AN_DEVAD,
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+ MDIO_AN_REG_8073_BAM, &val);
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+ bnx2x_cl45_write(bp, phy,
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+ MDIO_AN_DEVAD,
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+ MDIO_AN_REG_8073_BAM, val | 1);
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+ DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
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+ }
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if (params->loopback_mode == LOOPBACK_EXT) {
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bnx2x_807x_force_10G(bp, phy);
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DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
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@@ -5302,7 +5308,7 @@ static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
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{
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struct bnx2x *bp = params->bp;
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u16 autoneg_val, an_1000_val, an_10_100_val;
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- bnx2x_wait_reset_complete(bp, phy);
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+
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bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
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1 << NIG_LATCH_BC_ENABLE_MI_INT);
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@@ -5431,6 +5437,7 @@ static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
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/* HW reset */
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bnx2x_ext_phy_hw_reset(bp, params->port);
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+ bnx2x_wait_reset_complete(bp, phy);
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bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
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return bnx2x_848xx_cmn_config_init(phy, params, vars);
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@@ -5441,7 +5448,7 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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struct link_vars *vars)
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{
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struct bnx2x *bp = params->bp;
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- u8 port = params->port, initialize = 1;
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+ u8 port, initialize = 1;
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u16 val;
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u16 temp;
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u32 actual_phy_selection;
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@@ -5450,11 +5457,16 @@ static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
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/* This is just for MDIO_CTL_REG_84823_MEDIA register. */
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msleep(1);
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+ if (CHIP_IS_E2(bp))
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+ port = BP_PATH(bp);
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+ else
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+ port = params->port;
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
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MISC_REGISTERS_GPIO_OUTPUT_HIGH,
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port);
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- msleep(200); /* 100 is not enough */
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-
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+ bnx2x_wait_reset_complete(bp, phy);
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+ /* Wait for GPHY to come out of reset */
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+ msleep(50);
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/* BCM84823 requires that XGXS links up first @ 10G for normal
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behavior */
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temp = vars->line_speed;
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@@ -5625,7 +5637,11 @@ static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
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struct link_params *params)
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{
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struct bnx2x *bp = params->bp;
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- u8 port = params->port;
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+ u8 port;
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+ if (CHIP_IS_E2(bp))
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+ port = BP_PATH(bp);
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+ else
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+ port = params->port;
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bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
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MISC_REGISTERS_GPIO_OUTPUT_LOW,
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port);
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@@ -6928,7 +6944,7 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
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u8 reset_ext_phy)
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{
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struct bnx2x *bp = params->bp;
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- u8 phy_index, port = params->port;
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+ u8 phy_index, port = params->port, clear_latch_ind = 0;
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DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
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/* disable attentions */
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vars->link_status = 0;
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@@ -6966,9 +6982,18 @@ u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
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params->phy[phy_index].link_reset(
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¶ms->phy[phy_index],
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params);
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+ if (params->phy[phy_index].flags &
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+ FLAGS_REARM_LATCH_SIGNAL)
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+ clear_latch_ind = 1;
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}
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}
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+ if (clear_latch_ind) {
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+ /* Clear latching indication */
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+ bnx2x_rearm_latch_signal(bp, port, 0);
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+ bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
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+ 1 << NIG_LATCH_BC_ENABLE_MI_INT);
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+ }
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if (params->phy[INT_PHY].link_reset)
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params->phy[INT_PHY].link_reset(
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¶ms->phy[INT_PHY], params);
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@@ -6999,6 +7024,7 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
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s8 port;
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s8 port_of_path = 0;
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+ bnx2x_ext_phy_hw_reset(bp, 0);
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/* PART1 - Reset both phys */
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for (port = PORT_MAX - 1; port >= PORT_0; port--) {
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u32 shmem_base, shmem2_base;
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@@ -7021,7 +7047,8 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
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return -EINVAL;
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}
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/* disable attentions */
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- bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
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+ bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
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+ port_of_path*4,
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(NIG_MASK_XGXS0_LINK_STATUS |
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NIG_MASK_XGXS0_LINK10G |
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NIG_MASK_SERDES0_LINK_STATUS |
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@@ -7132,7 +7159,7 @@ static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
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(1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
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REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
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- bnx2x_ext_phy_hw_reset(bp, 1);
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+ bnx2x_ext_phy_hw_reset(bp, 0);
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msleep(5);
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for (port = 0; port < PORT_MAX; port++) {
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u32 shmem_base, shmem2_base;
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