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@@ -632,6 +632,22 @@ static void ar9003_hw_override_ini(struct ath_hw *ah)
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REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
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AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
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+
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+ if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
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+ REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
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+ AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
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+
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+ if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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+ AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
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+ ah->enabled_cals |= TX_IQ_CAL;
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+ else
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+ ah->enabled_cals &= ~TX_IQ_CAL;
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+
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+ if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
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+ ah->enabled_cals |= TX_CL_CAL;
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+ else
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+ ah->enabled_cals &= ~TX_CL_CAL;
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+ }
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}
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static void ar9003_hw_prog_ini(struct ath_hw *ah,
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@@ -814,29 +830,12 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
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if (chan->channel == 2484)
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ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
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- if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
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- REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
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- AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
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-
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ah->modes_index = modesIndex;
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ar9003_hw_override_ini(ah);
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ar9003_hw_set_channel_regs(ah, chan);
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ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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ath9k_hw_apply_txpower(ah, chan, false);
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- if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
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- if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
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- AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
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- ah->enabled_cals |= TX_IQ_CAL;
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- else
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- ah->enabled_cals &= ~TX_IQ_CAL;
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-
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- if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
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- ah->enabled_cals |= TX_CL_CAL;
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- else
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- ah->enabled_cals &= ~TX_CL_CAL;
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- }
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-
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return 0;
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}
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