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@@ -29,7 +29,7 @@ static void master_clk_init(struct clk *clk)
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clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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-static struct clk_ops sh7206_master_clk_ops = {
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+static struct sh_clk_ops sh7206_master_clk_ops = {
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.init = master_clk_init,
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};
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@@ -39,7 +39,7 @@ static unsigned long module_clk_recalc(struct clk *clk)
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return clk->parent->rate / pfc_divisors[idx];
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}
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-static struct clk_ops sh7206_module_clk_ops = {
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+static struct sh_clk_ops sh7206_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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@@ -48,7 +48,7 @@ static unsigned long bus_clk_recalc(struct clk *clk)
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return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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}
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-static struct clk_ops sh7206_bus_clk_ops = {
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+static struct sh_clk_ops sh7206_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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@@ -58,18 +58,18 @@ static unsigned long cpu_clk_recalc(struct clk *clk)
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return clk->parent->rate / ifc_divisors[idx];
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}
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-static struct clk_ops sh7206_cpu_clk_ops = {
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+static struct sh_clk_ops sh7206_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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-static struct clk_ops *sh7206_clk_ops[] = {
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+static struct sh_clk_ops *sh7206_clk_ops[] = {
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&sh7206_master_clk_ops,
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&sh7206_module_clk_ops,
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&sh7206_bus_clk_ops,
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&sh7206_cpu_clk_ops,
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};
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-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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+void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
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{
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if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
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pll2_mult = 1;
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