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@@ -1093,7 +1093,7 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
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* For each generation, we track the original measured
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* nanosecond time, offset, and write, so if TSCs are in
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* sync, we can match exact offset, and if not, we can match
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- * exact software computaion in compute_guest_tsc()
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+ * exact software computation in compute_guest_tsc()
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*
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* These values are tracked in kvm->arch.cur_xxx variables.
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*/
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@@ -1500,7 +1500,7 @@ static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
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{
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gpa_t gpa = data & ~0x3f;
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- /* Bits 2:5 are resrved, Should be zero */
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+ /* Bits 2:5 are reserved, Should be zero */
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if (data & 0x3c)
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return 1;
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@@ -1723,7 +1723,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
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* Ignore all writes to this no longer documented MSR.
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* Writes are only relevant for old K7 processors,
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* all pre-dating SVM, but a recommended workaround from
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- * AMD for these chips. It is possible to speicify the
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+ * AMD for these chips. It is possible to specify the
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* affected processor models on the command line, hence
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* the need to ignore the workaround.
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*/
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@@ -4491,7 +4491,7 @@ static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
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/*
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* if emulation was due to access to shadowed page table
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- * and it failed try to unshadow page and re-entetr the
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+ * and it failed try to unshadow page and re-enter the
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* guest to let CPU execute the instruction.
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*/
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if (kvm_mmu_unprotect_page_virt(vcpu, gva))
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@@ -5587,7 +5587,7 @@ int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
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/*
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* We are here if userspace calls get_regs() in the middle of
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* instruction emulation. Registers state needs to be copied
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- * back from emulation context to vcpu. Usrapace shouldn't do
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+ * back from emulation context to vcpu. Userspace shouldn't do
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* that usually, but some bad designed PV devices (vmware
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* backdoor interface) need this to work
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*/
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@@ -6116,7 +6116,7 @@ int kvm_arch_hardware_enable(void *garbage)
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* as we reset last_host_tsc on all VCPUs to stop this from being
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* called multiple times (one for each physical CPU bringup).
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*
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- * Platforms with unnreliable TSCs don't have to deal with this, they
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+ * Platforms with unreliable TSCs don't have to deal with this, they
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* will be compensated by the logic in vcpu_load, which sets the TSC to
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* catchup mode. This will catchup all VCPUs to real time, but cannot
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* guarantee that they stay in perfect synchronization.
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@@ -6391,7 +6391,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
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map_flags = MAP_SHARED | MAP_ANONYMOUS;
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/*To keep backward compatibility with older userspace,
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- *x86 needs to hanlde !user_alloc case.
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+ *x86 needs to handle !user_alloc case.
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*/
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if (!user_alloc) {
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if (npages && !old.rmap) {
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Guo Chao