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@@ -343,18 +343,34 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
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b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
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}
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+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
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+static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
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+{
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+ u32 tmslow;
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+
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+ if (dev->phy.type != B43_PHYTYPE_N)
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+ return;
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+
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+ tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
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+ if (force)
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+ tmslow |= SSB_TMSLOW_FGC;
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+ else
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+ tmslow &= ~SSB_TMSLOW_FGC;
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+ ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
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+}
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+
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+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
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static void b43_nphy_reset_cca(struct b43_wldev *dev)
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{
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u16 bbcfg;
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- ssb_write32(dev->dev, SSB_TMSLOW,
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- ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC);
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+ b43_nphy_bmac_clock_fgc(dev, 1);
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bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
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- b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
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- b43_phy_write(dev, B43_NPHY_BBCFG,
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- bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
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- ssb_write32(dev->dev, SSB_TMSLOW,
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- ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
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+ b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
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+ udelay(1);
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+ b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
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+ b43_nphy_bmac_clock_fgc(dev, 0);
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+ /* TODO: N PHY Force RF Seq with argument 2 */
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}
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enum b43_nphy_rf_sequence {
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