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@@ -2059,26 +2059,31 @@ static int __devinit check_position_fix(struct azx *chip, int fix)
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{
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{
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const struct snd_pci_quirk *q;
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const struct snd_pci_quirk *q;
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- /* Check VIA HD Audio Controller exist */
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- if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
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- chip->pci->device == VIA_HDAC_DEVICE_ID) {
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+ switch (fix) {
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+ case POS_FIX_LPIB:
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+ case POS_FIX_POSBUF:
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+ return fix;
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+ }
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+
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+ /* Check VIA/ATI HD Audio Controller exist */
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+ switch (chip->driver_type) {
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+ case AZX_DRIVER_VIA:
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+ case AZX_DRIVER_ATI:
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chip->via_dmapos_patch = 1;
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chip->via_dmapos_patch = 1;
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/* Use link position directly, avoid any transfer problem. */
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/* Use link position directly, avoid any transfer problem. */
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return POS_FIX_LPIB;
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return POS_FIX_LPIB;
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}
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}
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chip->via_dmapos_patch = 0;
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chip->via_dmapos_patch = 0;
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- if (fix == POS_FIX_AUTO) {
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- q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
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- if (q) {
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- printk(KERN_INFO
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- "hda_intel: position_fix set to %d "
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- "for device %04x:%04x\n",
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- q->value, q->subvendor, q->subdevice);
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- return q->value;
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- }
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+ q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
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+ if (q) {
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+ printk(KERN_INFO
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+ "hda_intel: position_fix set to %d "
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+ "for device %04x:%04x\n",
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+ q->value, q->subvendor, q->subdevice);
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+ return q->value;
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}
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}
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- return fix;
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+ return POS_FIX_AUTO;
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}
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}
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/*
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/*
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@@ -2221,9 +2226,17 @@ static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
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gcap = azx_readw(chip, GCAP);
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gcap = azx_readw(chip, GCAP);
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snd_printdd("chipset global capabilities = 0x%x\n", gcap);
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snd_printdd("chipset global capabilities = 0x%x\n", gcap);
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+ /* ATI chips seems buggy about 64bit DMA addresses */
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+ if (chip->driver_type == AZX_DRIVER_ATI)
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+ gcap &= ~0x01;
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+
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/* allow 64bit DMA address if supported by H/W */
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/* allow 64bit DMA address if supported by H/W */
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if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
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if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
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pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
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pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
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+ else {
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+ pci_set_dma_mask(pci, DMA_32BIT_MASK);
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+ pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK);
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+ }
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/* read number of streams from GCAP register instead of using
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/* read number of streams from GCAP register instead of using
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* hardcoded value
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* hardcoded value
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