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+/*
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+ * MIPS idle loop and WAIT instruction support.
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+ *
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+ * Copyright (C) xxxx the Anonymous
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+ * Copyright (C) 1994 - 2006 Ralf Baechle
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+ * Copyright (C) 2003, 2004 Maciej W. Rozycki
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+ * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version
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+ * 2 of the License, or (at your option) any later version.
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+ */
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+#include <linux/export.h>
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+#include <linux/init.h>
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+#include <linux/irqflags.h>
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+#include <linux/printk.h>
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+#include <linux/sched.h>
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+#include <asm/cpu.h>
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+#include <asm/cpu-info.h>
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+#include <asm/mipsregs.h>
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+
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+/*
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+ * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
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+ * the implementation of the "wait" feature differs between CPU families. This
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+ * points to the function that implements CPU specific wait.
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+ * The wait instruction stops the pipeline and reduces the power consumption of
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+ * the CPU very much.
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+ */
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+void (*cpu_wait)(void);
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+EXPORT_SYMBOL(cpu_wait);
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+
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+static void r3081_wait(void)
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+{
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+ unsigned long cfg = read_c0_conf();
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+ write_c0_conf(cfg | R30XX_CONF_HALT);
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+}
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+
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+static void r39xx_wait(void)
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+{
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+ local_irq_disable();
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+ if (!need_resched())
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+ write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
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+ local_irq_enable();
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+}
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+
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+extern void r4k_wait(void);
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+
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+/*
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+ * This variant is preferable as it allows testing need_resched and going to
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+ * sleep depending on the outcome atomically. Unfortunately the "It is
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+ * implementation-dependent whether the pipeline restarts when a non-enabled
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+ * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
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+ * using this version a gamble.
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+ */
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+void r4k_wait_irqoff(void)
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+{
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+ local_irq_disable();
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+ if (!need_resched())
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+ __asm__(" .set push \n"
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+ " .set mips3 \n"
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+ " wait \n"
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+ " .set pop \n");
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+ local_irq_enable();
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+ __asm__(" .globl __pastwait \n"
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+ "__pastwait: \n");
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+}
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+
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+/*
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+ * The RM7000 variant has to handle erratum 38. The workaround is to not
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+ * have any pending stores when the WAIT instruction is executed.
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+ */
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+static void rm7k_wait_irqoff(void)
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+{
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+ local_irq_disable();
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+ if (!need_resched())
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+ __asm__(
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+ " .set push \n"
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+ " .set mips3 \n"
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+ " .set noat \n"
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+ " mfc0 $1, $12 \n"
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+ " sync \n"
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+ " mtc0 $1, $12 # stalls until W stage \n"
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+ " wait \n"
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+ " mtc0 $1, $12 # stalls until W stage \n"
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+ " .set pop \n");
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+ local_irq_enable();
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+}
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+
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+/*
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+ * The Au1xxx wait is available only if using 32khz counter or
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+ * external timer source, but specifically not CP0 Counter.
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+ * alchemy/common/time.c may override cpu_wait!
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+ */
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+static void au1k_wait(void)
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+{
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+ __asm__(" .set mips3 \n"
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+ " cache 0x14, 0(%0) \n"
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+ " cache 0x14, 32(%0) \n"
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+ " sync \n"
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+ " nop \n"
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+ " wait \n"
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+ " nop \n"
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+ " nop \n"
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+ " nop \n"
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+ " nop \n"
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+ " .set mips0 \n"
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+ : : "r" (au1k_wait));
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+}
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+
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+static int __initdata nowait;
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+
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+static int __init wait_disable(char *s)
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+{
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+ nowait = 1;
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+
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+ return 1;
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+}
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+
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+__setup("nowait", wait_disable);
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+
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+void __init check_wait(void)
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+{
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+ struct cpuinfo_mips *c = ¤t_cpu_data;
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+
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+ if (nowait) {
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+ printk("Wait instruction disabled.\n");
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+ return;
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+ }
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+
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+ switch (c->cputype) {
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+ case CPU_R3081:
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+ case CPU_R3081E:
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+ cpu_wait = r3081_wait;
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+ break;
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+ case CPU_TX3927:
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+ cpu_wait = r39xx_wait;
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+ break;
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+ case CPU_R4200:
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+/* case CPU_R4300: */
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+ case CPU_R4600:
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+ case CPU_R4640:
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+ case CPU_R4650:
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+ case CPU_R4700:
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+ case CPU_R5000:
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+ case CPU_R5500:
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+ case CPU_NEVADA:
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+ case CPU_4KC:
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+ case CPU_4KEC:
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+ case CPU_4KSC:
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+ case CPU_5KC:
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+ case CPU_25KF:
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+ case CPU_PR4450:
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+ case CPU_BMIPS3300:
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+ case CPU_BMIPS4350:
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+ case CPU_BMIPS4380:
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+ case CPU_BMIPS5000:
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+ case CPU_CAVIUM_OCTEON:
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+ case CPU_CAVIUM_OCTEON_PLUS:
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+ case CPU_CAVIUM_OCTEON2:
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+ case CPU_JZRISC:
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+ case CPU_LOONGSON1:
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+ case CPU_XLR:
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+ case CPU_XLP:
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+ cpu_wait = r4k_wait;
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+ break;
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+
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+ case CPU_RM7000:
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+ cpu_wait = rm7k_wait_irqoff;
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+ break;
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+
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+ case CPU_M14KC:
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+ case CPU_M14KEC:
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+ case CPU_24K:
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+ case CPU_34K:
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+ case CPU_1004K:
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+ cpu_wait = r4k_wait;
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+ if (read_c0_config7() & MIPS_CONF7_WII)
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+ cpu_wait = r4k_wait_irqoff;
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+ break;
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+
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+ case CPU_74K:
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+ cpu_wait = r4k_wait;
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+ if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
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+ cpu_wait = r4k_wait_irqoff;
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+ break;
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+
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+ case CPU_TX49XX:
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+ cpu_wait = r4k_wait_irqoff;
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+ break;
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+ case CPU_ALCHEMY:
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+ cpu_wait = au1k_wait;
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+ break;
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+ case CPU_20KC:
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+ /*
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+ * WAIT on Rev1.0 has E1, E2, E3 and E16.
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+ * WAIT on Rev2.0 and Rev3.0 has E16.
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+ * Rev3.1 WAIT is nop, why bother
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+ */
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+ if ((c->processor_id & 0xff) <= 0x64)
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+ break;
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+
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+ /*
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+ * Another rev is incremeting c0_count at a reduced clock
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+ * rate while in WAIT mode. So we basically have the choice
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+ * between using the cp0 timer as clocksource or avoiding
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+ * the WAIT instruction. Until more details are known,
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+ * disable the use of WAIT for 20Kc entirely.
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+ cpu_wait = r4k_wait;
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+ */
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+ break;
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+ case CPU_RM9000:
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+ if ((c->processor_id & 0x00ff) >= 0x40)
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+ cpu_wait = r4k_wait;
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+
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+void arch_cpu_idle(void)
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+{
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+#ifdef CONFIG_MIPS_MT_SMTC
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+ extern void smtc_idle_loop_hook(void);
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+
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+ smtc_idle_loop_hook();
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+#endif
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+ if (cpu_wait)
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+ (*cpu_wait)();
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+ else
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+ local_irq_enable();
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+}
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Ralf Baechle