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@@ -1160,7 +1160,7 @@ de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
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sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
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lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
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-#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
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+#if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
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lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
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#endif
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lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
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@@ -1175,7 +1175,7 @@ de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
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** Set up the RX descriptor ring (Intels)
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** Allocate contiguous receive buffers, long word aligned (Alphas)
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*/
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-#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
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+#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
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for (i=0; i<NUM_RX_DESC; i++) {
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lp->rx_ring[i].status = 0;
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lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
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@@ -1252,11 +1252,7 @@ de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
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mii_get_phy(dev);
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}
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-#ifndef __sparc_v9__
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printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
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-#else
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- printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
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-#endif
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((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
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}
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@@ -3627,7 +3623,7 @@ de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
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struct de4x5_private *lp = netdev_priv(dev);
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struct sk_buff *p;
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-#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
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+#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
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struct sk_buff *ret;
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u_long i=0, tmp;
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