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@@ -1403,14 +1403,18 @@ out_unlock:
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static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
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{
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struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
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- struct intel_pch_pll *pll = intel_crtc->pch_pll;
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+ struct intel_pch_pll *pll;
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int reg;
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u32 val;
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- /* PCH only available on ILK+ */
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+ /* PCH PLLs only available on ILK, SNB and IVB */
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BUG_ON(dev_priv->info->gen < 5);
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- BUG_ON(pll == NULL);
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- BUG_ON(pll->refcount == 0);
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+ pll = intel_crtc->pch_pll;
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+ if (pll == NULL)
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+ return;
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+
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+ if (WARN_ON(pll->refcount == 0))
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+ return;
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DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
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pll->pll_reg, pll->active, pll->on,
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@@ -1448,13 +1452,18 @@ static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
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if (pll == NULL)
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return;
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- BUG_ON(pll->refcount == 0);
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+ if (WARN_ON(pll->refcount == 0))
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+ return;
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DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
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pll->pll_reg, pll->active, pll->on,
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intel_crtc->base.base.id);
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- BUG_ON(pll->active == 0);
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+ if (WARN_ON(pll->active == 0)) {
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+ assert_pch_pll_disabled(dev_priv, intel_crtc);
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+ return;
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+ }
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+
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if (--pll->active) {
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assert_pch_pll_enabled(dev_priv, intel_crtc);
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return;
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