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@@ -96,132 +96,8 @@ static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
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return -EINVAL;
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}
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-/**
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- * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
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- */
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-void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
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- struct iwl_tx_queue *txq,
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- u16 byte_cnt)
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-{
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- struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
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- int write_ptr = txq->q.write_ptr;
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- int txq_id = txq->q.id;
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- u8 sec_ctl = 0;
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- u8 sta_id = 0;
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- u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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- __le16 bc_ent;
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-
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- WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
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-
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- sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
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- sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
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-
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- switch (sec_ctl & TX_CMD_SEC_MSK) {
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- case TX_CMD_SEC_CCM:
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- len += CCMP_MIC_LEN;
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- break;
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- case TX_CMD_SEC_TKIP:
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- len += TKIP_ICV_LEN;
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- break;
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- case TX_CMD_SEC_WEP:
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- len += WEP_IV_LEN + WEP_ICV_LEN;
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- break;
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- }
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-
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- bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
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-
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- scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
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-
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- if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
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- scd_bc_tbl[txq_id].
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- tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
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-}
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-
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-static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
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- struct iwl_tx_queue *txq)
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-{
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- struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
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- int txq_id = txq->q.id;
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- int read_ptr = txq->q.read_ptr;
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- u8 sta_id = 0;
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- __le16 bc_ent;
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-
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- WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
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-
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- if (txq_id != priv->cmd_queue)
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- sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
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-
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- bc_ent = cpu_to_le16(1 | (sta_id << 12));
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- scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
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-
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- if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
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- scd_bc_tbl[txq_id].
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- tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
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-}
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-
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-static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
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- u16 txq_id)
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-{
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- u32 tbl_dw_addr;
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- u32 tbl_dw;
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- u16 scd_q2ratid;
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-
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- scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
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-
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- tbl_dw_addr = priv->scd_base_addr +
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- SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
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-
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- tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
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-
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- if (txq_id & 0x1)
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- tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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- else
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- tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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-
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- iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
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-
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- return 0;
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-}
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-
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-static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
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-{
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- /* Simply stop the queue, but don't change any configuration;
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- * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
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- iwl_write_prph(priv,
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- SCD_QUEUE_STATUS_BITS(txq_id),
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- (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
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- (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
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-}
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-
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-void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
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- int txq_id, u32 index)
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-{
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- iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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- (index & 0xff) | (txq_id << 8));
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- iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
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-}
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-
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-void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
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- struct iwl_tx_queue *txq,
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- int tx_fifo_id, int scd_retry)
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-{
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- int txq_id = txq->q.id;
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- int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
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-
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- iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id),
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- (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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- (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
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- (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
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- SCD_QUEUE_STTS_REG_MSK);
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-
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- txq->sched_retry = scd_retry;
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-
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- IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
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- active ? "Activate" : "Deactivate",
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- scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
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-}
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-
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-static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id, int tid)
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+static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id,
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+ int tid)
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{
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if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
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(IWLAGN_FIRST_AMPDU_QUEUE +
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@@ -238,99 +114,6 @@ static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id,
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return iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
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}
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-void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv,
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- struct ieee80211_sta *sta,
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- int tid, int frame_limit)
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-{
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- int sta_id, tx_fifo, txq_id, ssn_idx;
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- u16 ra_tid;
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- unsigned long flags;
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- struct iwl_tid_data *tid_data;
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-
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- sta_id = iwl_sta_id(sta);
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- if (WARN_ON(sta_id == IWL_INVALID_STATION))
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- return;
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- if (WARN_ON(tid >= MAX_TID_COUNT))
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- return;
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-
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- spin_lock_irqsave(&priv->sta_lock, flags);
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- tid_data = &priv->stations[sta_id].tid[tid];
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- ssn_idx = SEQ_TO_SN(tid_data->seq_number);
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- txq_id = tid_data->agg.txq_id;
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- tx_fifo = tid_data->agg.tx_fifo;
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- spin_unlock_irqrestore(&priv->sta_lock, flags);
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-
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- ra_tid = BUILD_RAxTID(sta_id, tid);
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-
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- spin_lock_irqsave(&priv->lock, flags);
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-
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- /* Stop this Tx queue before configuring it */
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- iwlagn_tx_queue_stop_scheduler(priv, txq_id);
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-
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- /* Map receiver-address / traffic-ID to this queue */
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- iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
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-
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- /* Set this queue as a chain-building queue */
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- iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
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-
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- /* enable aggregations for the queue */
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- iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id));
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-
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- /* Place first TFD at index corresponding to start sequence number.
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- * Assumes that ssn_idx is valid (!= 0xFFF) */
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- priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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- priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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- iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
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-
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- /* Set up Tx window size and frame limit for this queue */
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- iwl_write_targ_mem(priv, priv->scd_base_addr +
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- SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
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- sizeof(u32),
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- ((frame_limit <<
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- SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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- SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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- ((frame_limit <<
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- SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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- SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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-
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- iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
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-
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- /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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- iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
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-
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- spin_unlock_irqrestore(&priv->lock, flags);
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-}
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-
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-static int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
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- u16 ssn_idx, u8 tx_fifo)
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-{
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- if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
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- (IWLAGN_FIRST_AMPDU_QUEUE +
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- priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
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- IWL_ERR(priv,
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- "queue number out of range: %d, must be %d to %d\n",
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- txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
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- IWLAGN_FIRST_AMPDU_QUEUE +
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- priv->cfg->base_params->num_of_ampdu_queues - 1);
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- return -EINVAL;
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- }
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-
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- iwlagn_tx_queue_stop_scheduler(priv, txq_id);
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-
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- iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id));
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-
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- priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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- priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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- /* supposes that ssn_idx is valid (!= 0xFFF) */
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- iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
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-
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- iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
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- iwl_txq_ctx_deactivate(priv, txq_id);
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- iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
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-
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- return 0;
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-}
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-
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static void iwlagn_tx_cmd_protection(struct iwl_priv *priv,
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struct ieee80211_tx_info *info,
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__le16 fc, __le32 *tx_flags)
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@@ -850,7 +633,7 @@ int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
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* to deactivate the uCode queue, just return "success" to allow
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* mac80211 to clean up it own data.
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*/
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- iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo_id);
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+ trans_txq_agg_disable(priv, txq_id, ssn, tx_fifo_id);
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spin_unlock_irqrestore(&priv->lock, flags);
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ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
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@@ -879,7 +662,7 @@ int iwlagn_txq_check_empty(struct iwl_priv *priv,
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u16 ssn = SEQ_TO_SN(tid_data->seq_number);
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int tx_fifo = get_fifo_from_tid(ctx, tid);
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IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
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- iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo);
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+ trans_txq_agg_disable(priv, txq_id, ssn, tx_fifo);
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tid_data->agg.state = IWL_AGG_OFF;
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ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
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}
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