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@@ -29,6 +29,7 @@
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_device.h>
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+#include <linux/phy.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <linux/sh_eth.h>
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@@ -155,6 +156,30 @@ static void __init lager_add_standard_devices(void)
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ðer_pdata, sizeof(ether_pdata));
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}
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+/*
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+ * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
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+ * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
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+ * 14-15. We have to set them back to 01 from the default 00 value each time
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+ * the PHY is reset. It's also important because the PHY's LED0 signal is
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+ * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
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+ * bounce on and off after each packet, which we apparently want to avoid.
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+ */
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+static int lager_ksz8041_fixup(struct phy_device *phydev)
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+{
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+ u16 phyctrl1 = phy_read(phydev, 0x1e);
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+
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+ phyctrl1 &= ~0xc000;
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+ phyctrl1 |= 0x4000;
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+ return phy_write(phydev, 0x1e, phyctrl1);
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+}
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+
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+static void __init lager_init(void)
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+{
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+ lager_add_standard_devices();
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+
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+ phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
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+}
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+
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static const char *lager_boards_compat_dt[] __initdata = {
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"renesas,lager",
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NULL,
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@@ -163,6 +188,6 @@ static const char *lager_boards_compat_dt[] __initdata = {
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DT_MACHINE_START(LAGER_DT, "lager")
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.init_early = r8a7790_init_delay,
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.init_time = r8a7790_timer_init,
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- .init_machine = lager_add_standard_devices,
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+ .init_machine = lager_init,
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.dt_compat = lager_boards_compat_dt,
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MACHINE_END
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