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@@ -3,9 +3,9 @@
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/*
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/*
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* SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
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* SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
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- * Support for 16 and 64-bit accesses are done through shifting and
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- * masking relative to the endianness. Unaligned stores are not supported
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- * by the instruction encoding, so these continue to use the packed
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+ * Support for 64-bit accesses are done through shifting and masking
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+ * relative to the endianness. Unaligned stores are not supported by the
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+ * instruction encoding, so these continue to use the packed
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* struct.
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* struct.
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*
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*
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* The same note as with the movli.l/movco.l pair applies here, as long
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* The same note as with the movli.l/movco.l pair applies here, as long
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@@ -41,9 +41,9 @@ struct __una_u64 { u64 x __attribute__((packed)); };
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static inline u16 __get_unaligned_cpu16(const u8 *p)
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static inline u16 __get_unaligned_cpu16(const u8 *p)
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{
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{
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#ifdef __LITTLE_ENDIAN
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#ifdef __LITTLE_ENDIAN
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- return __get_unaligned_cpu32(p) & 0xffff;
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+ return p[0] | p[1] << 8;
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#else
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#else
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- return __get_unaligned_cpu32(p) >> 16;
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+ return p[0] << 8 | p[1];
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#endif
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#endif
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}
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}
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