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@@ -1258,7 +1258,15 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
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/* Ack/clear/reset pending uCode interrupts.
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* Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
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*/
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- iwl_write32(priv, CSR_INT, priv->inta);
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+ /* There is a hardware bug in the interrupt mask function that some
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+ * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
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+ * they are disabled in the CSR_INT_MASK register. Furthermore the
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+ * ICT interrupt handling mechanism has another bug that might cause
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+ * these unmasked interrupts fail to be detected. We workaround the
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+ * hardware bugs here by ACKing all the possible interrupts so that
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+ * interrupt coalescing can still be achieved.
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+ */
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+ iwl_write32(priv, CSR_INT, priv->inta | ~priv->inta_mask);
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inta = priv->inta;
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