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@@ -0,0 +1,316 @@
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+/*
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+ * System timer for CSR SiRFprimaII
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+ *
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+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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+ *
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+ * Licensed under GPLv2 or later.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/interrupt.h>
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+#include <linux/clockchips.h>
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+#include <linux/clocksource.h>
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+#include <linux/bitops.h>
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+#include <linux/irq.h>
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+#include <linux/clk.h>
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+#include <linux/slab.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_address.h>
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+#include <asm/sched_clock.h>
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+#include <asm/localtimer.h>
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+#include <asm/mach/time.h>
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+
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+#include "common.h"
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+
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+#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
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+#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
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+#define SIRFSOC_TIMER_MATCH_0 0x0018
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+#define SIRFSOC_TIMER_MATCH_1 0x001c
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+#define SIRFSOC_TIMER_COUNTER_0 0x0048
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+#define SIRFSOC_TIMER_COUNTER_1 0x004c
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+#define SIRFSOC_TIMER_INTR_STATUS 0x0060
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+#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
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+#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
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+#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
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+#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
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+#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
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+#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
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+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
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+#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
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+
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+#define SIRFSOC_TIMER_REG_CNT 6
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+
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+static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
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+ SIRFSOC_TIMER_WATCHDOG_EN,
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+ SIRFSOC_TIMER_32COUNTER_0_CTRL,
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+ SIRFSOC_TIMER_32COUNTER_1_CTRL,
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+ SIRFSOC_TIMER_64COUNTER_CTRL,
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+ SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
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+ SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
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+};
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+
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+static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
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+
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+static void __iomem *sirfsoc_timer_base;
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+static void __init sirfsoc_of_timer_map(void);
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+
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+/* disable count and interrupt */
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+static inline void sirfsoc_timer_count_disable(int idx)
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+{
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+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
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+ sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
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+}
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+
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+/* enable count and interrupt */
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+static inline void sirfsoc_timer_count_enable(int idx)
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+{
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+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
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+ sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
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+}
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+
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+/* timer interrupt handler */
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+static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
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+{
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+ struct clock_event_device *ce = dev_id;
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+ int cpu = smp_processor_id();
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+
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+ /* clear timer interrupt */
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+ writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
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+
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+ if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
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+ sirfsoc_timer_count_disable(cpu);
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+
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+ ce->event_handler(ce);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+/* read 64-bit timer counter */
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+static cycle_t sirfsoc_timer_read(struct clocksource *cs)
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+{
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+ u64 cycles;
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+
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+ writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
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+ BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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+
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+ cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
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+ cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
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+
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+ return cycles;
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+}
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+
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+static int sirfsoc_timer_set_next_event(unsigned long delta,
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+ struct clock_event_device *ce)
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+{
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+ int cpu = smp_processor_id();
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+
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+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
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+ 4 * cpu);
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+ writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
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+ 4 * cpu);
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+
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+ /* enable the tick */
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+ sirfsoc_timer_count_enable(cpu);
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+
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+ return 0;
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+}
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+
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+static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
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+ struct clock_event_device *ce)
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+{
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+ switch (mode) {
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+ case CLOCK_EVT_MODE_ONESHOT:
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+ /* enable in set_next_event */
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ sirfsoc_timer_count_disable(smp_processor_id());
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+}
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+
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+static void sirfsoc_clocksource_suspend(struct clocksource *cs)
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+{
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+ int i;
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+
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+ for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
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+ sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
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+}
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+
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+static void sirfsoc_clocksource_resume(struct clocksource *cs)
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+{
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+ int i;
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+
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+ for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
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+ writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
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+
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+ writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
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+ sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
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+ writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
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+ sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
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+
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+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
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+ BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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+}
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+
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+static struct clock_event_device sirfsoc_clockevent = {
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+ .name = "sirfsoc_clockevent",
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+ .rating = 200,
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+ .features = CLOCK_EVT_FEAT_ONESHOT,
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+ .set_mode = sirfsoc_timer_set_mode,
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+ .set_next_event = sirfsoc_timer_set_next_event,
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+};
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+
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+static struct clocksource sirfsoc_clocksource = {
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+ .name = "sirfsoc_clocksource",
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+ .rating = 200,
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+ .mask = CLOCKSOURCE_MASK(64),
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+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
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+ .read = sirfsoc_timer_read,
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+ .suspend = sirfsoc_clocksource_suspend,
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+ .resume = sirfsoc_clocksource_resume,
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+};
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+
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+static struct irqaction sirfsoc_timer_irq = {
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+ .name = "sirfsoc_timer0",
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+ .flags = IRQF_TIMER | IRQF_NOBALANCING,
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+ .handler = sirfsoc_timer_interrupt,
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+ .dev_id = &sirfsoc_clockevent,
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+};
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+
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+#ifdef CONFIG_LOCAL_TIMERS
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+
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+static struct irqaction sirfsoc_timer1_irq = {
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+ .name = "sirfsoc_timer1",
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+ .flags = IRQF_TIMER | IRQF_NOBALANCING,
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+ .handler = sirfsoc_timer_interrupt,
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+};
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+
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+static int __cpuinit sirfsoc_local_timer_setup(struct clock_event_device *ce)
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+{
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+ /* Use existing clock_event for cpu 0 */
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+ if (!smp_processor_id())
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+ return 0;
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+
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+ ce->irq = sirfsoc_timer1_irq.irq;
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+ ce->name = "local_timer";
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+ ce->features = sirfsoc_clockevent.features;
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+ ce->rating = sirfsoc_clockevent.rating;
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+ ce->set_mode = sirfsoc_timer_set_mode;
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+ ce->set_next_event = sirfsoc_timer_set_next_event;
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+ ce->shift = sirfsoc_clockevent.shift;
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+ ce->mult = sirfsoc_clockevent.mult;
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+ ce->max_delta_ns = sirfsoc_clockevent.max_delta_ns;
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+ ce->min_delta_ns = sirfsoc_clockevent.min_delta_ns;
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+
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+ sirfsoc_timer1_irq.dev_id = ce;
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+ BUG_ON(setup_irq(ce->irq, &sirfsoc_timer1_irq));
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+ irq_set_affinity(sirfsoc_timer1_irq.irq, cpumask_of(1));
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+
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+ clockevents_register_device(ce);
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+ return 0;
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+}
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+
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+static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
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+{
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+ sirfsoc_timer_count_disable(1);
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+
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+ remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
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+}
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+
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+static struct local_timer_ops sirfsoc_local_timer_ops __cpuinitdata = {
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+ .setup = sirfsoc_local_timer_setup,
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+ .stop = sirfsoc_local_timer_stop,
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+};
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+#endif /* CONFIG_LOCAL_TIMERS */
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+
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+static void __init sirfsoc_clockevent_init(void)
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+{
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+ clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
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+
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+ sirfsoc_clockevent.max_delta_ns =
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+ clockevent_delta2ns(-2, &sirfsoc_clockevent);
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+ sirfsoc_clockevent.min_delta_ns =
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+ clockevent_delta2ns(2, &sirfsoc_clockevent);
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+
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+ sirfsoc_clockevent.cpumask = cpumask_of(0);
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+ clockevents_register_device(&sirfsoc_clockevent);
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+#ifdef CONFIG_LOCAL_TIMERS
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+ local_timer_register(&sirfsoc_local_timer_ops);
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+#endif
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+}
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+
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+/* initialize the kernel jiffy timer source */
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+void __init sirfsoc_marco_timer_init(void)
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+{
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+ unsigned long rate;
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+ u32 timer_div;
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+ struct clk *clk;
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+
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+ /* initialize clocking early, we want to set the OS timer */
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+ sirfsoc_of_clk_init();
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+
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+ /* timer's input clock is io clock */
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+ clk = clk_get_sys("io", NULL);
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+
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+ BUG_ON(IS_ERR(clk));
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+ rate = clk_get_rate(clk);
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+
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+ BUG_ON(rate < CLOCK_TICK_RATE);
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+ BUG_ON(rate % CLOCK_TICK_RATE);
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+
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+ sirfsoc_of_timer_map();
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+
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+ /* Initialize the timer dividers */
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+ timer_div = rate / CLOCK_TICK_RATE - 1;
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+ writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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+ writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
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+ writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
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+
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+ /* Initialize timer counters to 0 */
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+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
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+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
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+ writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
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+ BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
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+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
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+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
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+
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+ /* Clear all interrupts */
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+ writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
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+
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+ BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
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+
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+ BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
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+
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+ sirfsoc_clockevent_init();
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+}
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+
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+static struct of_device_id timer_ids[] = {
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+ { .compatible = "sirf,marco-tick" },
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+ {},
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+};
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+
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+static void __init sirfsoc_of_timer_map(void)
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+{
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+ struct device_node *np;
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+
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+ np = of_find_matching_node(NULL, timer_ids);
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+ if (!np)
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+ return;
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+ sirfsoc_timer_base = of_iomap(np, 0);
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+ if (!sirfsoc_timer_base)
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+ panic("unable to map timer cpu registers\n");
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+
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+ sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
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+ if (!sirfsoc_timer_irq.irq)
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+ panic("No irq passed for timer0 via DT\n");
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+
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+#ifdef CONFIG_LOCAL_TIMERS
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+ sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
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+ if (!sirfsoc_timer1_irq.irq)
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+ panic("No irq passed for timer1 via DT\n");
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+#endif
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+
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+ of_node_put(np);
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+}
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Barry Song