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@@ -5238,6 +5238,55 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
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.page_flip = intel_crtc_page_flip,
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};
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+static void intel_sanitize_modesetting(struct drm_device *dev,
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+ int pipe, int plane)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+ u32 reg, val;
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+
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+ if (HAS_PCH_SPLIT(dev))
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+ return;
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+
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+ /* Who knows what state these registers were left in by the BIOS or
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+ * grub?
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+ *
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+ * If we leave the registers in a conflicting state (e.g. with the
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+ * display plane reading from the other pipe than the one we intend
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+ * to use) then when we attempt to teardown the active mode, we will
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+ * not disable the pipes and planes in the correct order -- leaving
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+ * a plane reading from a disabled pipe and possibly leading to
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+ * undefined behaviour.
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+ */
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+
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+ reg = DSPCNTR(plane);
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+ val = I915_READ(reg);
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+
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+ if ((val & DISPLAY_PLANE_ENABLE) == 0)
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+ return;
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+ if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
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+ return;
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+
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+ /* This display plane is active and attached to the other CPU pipe. */
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+ pipe = !pipe;
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+
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+ /* Disable the plane and wait for it to stop reading from the pipe. */
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+ I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
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+ intel_flush_display_plane(dev, plane);
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+
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+ if (IS_GEN2(dev))
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+ intel_wait_for_vblank(dev, pipe);
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+
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+ if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
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+ return;
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+
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+ /* Switch off the pipe. */
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+ reg = PIPECONF(pipe);
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+ val = I915_READ(reg);
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+ if (val & PIPECONF_ENABLE) {
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+ I915_WRITE(reg, val & ~PIPECONF_ENABLE);
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+ intel_wait_for_pipe_off(dev, pipe);
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+ }
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+}
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static void intel_crtc_init(struct drm_device *dev, int pipe)
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{
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@@ -5289,6 +5338,8 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
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setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
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(unsigned long)intel_crtc);
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+
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+ intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
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}
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int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
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