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@@ -781,3 +781,22 @@ config ARM_L1_CACHE_SHIFT
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int
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default 6 if ARM_L1_CACHE_SHIFT_6
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default 5
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+
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+config ARM_DMA_MEM_BUFFERABLE
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+ bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
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+ default y if CPU_V6 || CPU_V7
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+ help
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+ Historically, the kernel has used strongly ordered mappings to
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+ provide DMA coherent memory. With the advent of ARMv7, mapping
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+ memory with differing types results in unpredictable behaviour,
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+ so on these CPUs, this option is forced on.
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+
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+ Multiple mappings with differing attributes is also unpredictable
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+ on ARMv6 CPUs, but since they do not have aggressive speculative
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+ prefetch, no harm appears to occur.
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+
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+ However, drivers may be missing the necessary barriers for ARMv6,
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+ and therefore turning this on may result in unpredictable driver
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+ behaviour. Therefore, we offer this as an option.
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+
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+ You are recommended say 'Y' here and debug any affected drivers.
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