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@@ -39,7 +39,8 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
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struct nouveau_dmaobj *dmaobj,
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struct nouveau_gpuobj **pgpuobj)
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{
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- int ret = 0;
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+ u32 flags0 = 0x00000000;
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+ int ret;
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if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
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switch (nv_mclass(parent->parent)) {
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@@ -50,6 +51,38 @@ nvd0_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
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} else
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return 0;
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+ if (!(dmaobj->conf0 & NVD0_DMA_CONF0_ENABLE)) {
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+ if (dmaobj->target == NV_MEM_TARGET_VM) {
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+ dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_VM;
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+ dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_LP;
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+ } else {
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+ dmaobj->conf0 |= NVD0_DMA_CONF0_TYPE_LINEAR;
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+ dmaobj->conf0 |= NVD0_DMA_CONF0_PAGE_SP;
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+ }
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+ }
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+
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+ flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_TYPE) << 20;
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+ flags0 |= (dmaobj->conf0 & NVD0_DMA_CONF0_PAGE) >> 4;
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+
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+ switch (dmaobj->target) {
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+ case NV_MEM_TARGET_VRAM:
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+ flags0 |= 0x00000009;
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+ break;
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+ default:
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+ return -EINVAL;
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+ break;
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+ }
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+
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+ ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
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+ if (ret == 0) {
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+ nv_wo32(*pgpuobj, 0x00, flags0);
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+ nv_wo32(*pgpuobj, 0x04, dmaobj->start >> 8);
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+ nv_wo32(*pgpuobj, 0x08, dmaobj->limit >> 8);
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+ nv_wo32(*pgpuobj, 0x0c, 0x00000000);
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+ nv_wo32(*pgpuobj, 0x10, 0x00000000);
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+ nv_wo32(*pgpuobj, 0x14, 0x00000000);
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+ }
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+
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return ret;
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}
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