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@@ -1,980 +0,0 @@
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-/*
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- * Copyright (c) 2010 Broadcom Corporation
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- *
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- * Permission to use, copy, modify, and/or distribute this software for any
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- * purpose with or without fee is hereby granted, provided that the above
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- * copyright notice and this permission notice appear in all copies.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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- */
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-
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-#include <linux/kernel.h>
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-#include <linux/string.h>
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-#include <linux/io.h>
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-#include <linux/etherdevice.h>
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-#include <linux/crc8.h>
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-#include <stdarg.h>
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-
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-#include <chipcommon.h>
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-#include <brcmu_utils.h>
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-#include "pub.h"
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-#include "nicpci.h"
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-#include "aiutils.h"
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-#include "otp.h"
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-#include "srom.h"
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-#include "soc.h"
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-
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-/*
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- * SROM CRC8 polynomial value:
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- *
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- * x^8 + x^7 +x^6 + x^4 + x^2 + 1
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- */
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-#define SROM_CRC8_POLY 0xAB
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-
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-/* Maximum srom: 6 Kilobits == 768 bytes */
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-#define SROM_MAX 768
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-
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-/* PCI fields */
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-#define PCI_F0DEVID 48
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-
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-#define SROM_WORDS 64
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-
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-#define SROM_SSID 2
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-
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-#define SROM_WL1LHMAXP 29
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-
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-#define SROM_WL1LPAB0 30
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-#define SROM_WL1LPAB1 31
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-#define SROM_WL1LPAB2 32
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-
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-#define SROM_WL1HPAB0 33
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-#define SROM_WL1HPAB1 34
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-#define SROM_WL1HPAB2 35
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-
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-#define SROM_MACHI_IL0 36
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-#define SROM_MACMID_IL0 37
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-#define SROM_MACLO_IL0 38
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-#define SROM_MACHI_ET1 42
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-#define SROM_MACMID_ET1 43
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-#define SROM_MACLO_ET1 44
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-
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-#define SROM_BXARSSI2G 40
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-#define SROM_BXARSSI5G 41
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-
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-#define SROM_TRI52G 42
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-#define SROM_TRI5GHL 43
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-
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-#define SROM_RXPO52G 45
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-
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-#define SROM_AABREV 46
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-/* Fields in AABREV */
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-#define SROM_BR_MASK 0x00ff
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-#define SROM_CC_MASK 0x0f00
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-#define SROM_CC_SHIFT 8
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-#define SROM_AA0_MASK 0x3000
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-#define SROM_AA0_SHIFT 12
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-#define SROM_AA1_MASK 0xc000
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-#define SROM_AA1_SHIFT 14
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-
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-#define SROM_WL0PAB0 47
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-#define SROM_WL0PAB1 48
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-#define SROM_WL0PAB2 49
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-
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-#define SROM_LEDBH10 50
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-#define SROM_LEDBH32 51
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-
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-#define SROM_WL10MAXP 52
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-
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-#define SROM_WL1PAB0 53
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-#define SROM_WL1PAB1 54
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-#define SROM_WL1PAB2 55
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-
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-#define SROM_ITT 56
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-
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-#define SROM_BFL 57
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-#define SROM_BFL2 28
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-
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-#define SROM_AG10 58
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-
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-#define SROM_CCODE 59
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-
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-#define SROM_OPO 60
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-
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-#define SROM_CRCREV 63
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-
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-#define SROM4_WORDS 220
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-
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-#define SROM4_TXCHAIN_MASK 0x000f
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-#define SROM4_RXCHAIN_MASK 0x00f0
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-#define SROM4_SWITCH_MASK 0xff00
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-
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-/* Per-path fields */
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-#define MAX_PATH_SROM 4
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-
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-#define SROM4_CRCREV 219
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-
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-/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
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- * This is acombined srom for both MIMO and SISO boards, usable in
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- * the .130 4Kilobit OTP with hardware redundancy.
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- */
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-#define SROM8_BREV 65
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-
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-#define SROM8_BFL0 66
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-#define SROM8_BFL1 67
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-#define SROM8_BFL2 68
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-#define SROM8_BFL3 69
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-
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-#define SROM8_MACHI 70
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-#define SROM8_MACMID 71
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-#define SROM8_MACLO 72
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-
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-#define SROM8_CCODE 73
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-#define SROM8_REGREV 74
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-
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-#define SROM8_LEDBH10 75
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-#define SROM8_LEDBH32 76
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-
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-#define SROM8_LEDDC 77
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-
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-#define SROM8_AA 78
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-
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-#define SROM8_AG10 79
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-#define SROM8_AG32 80
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-
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-#define SROM8_TXRXC 81
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-
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-#define SROM8_BXARSSI2G 82
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-#define SROM8_BXARSSI5G 83
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-#define SROM8_TRI52G 84
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-#define SROM8_TRI5GHL 85
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-#define SROM8_RXPO52G 86
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-
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-#define SROM8_FEM2G 87
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-#define SROM8_FEM5G 88
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-#define SROM8_FEM_ANTSWLUT_MASK 0xf800
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-#define SROM8_FEM_ANTSWLUT_SHIFT 11
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-#define SROM8_FEM_TR_ISO_MASK 0x0700
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-#define SROM8_FEM_TR_ISO_SHIFT 8
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-#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
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-#define SROM8_FEM_PDET_RANGE_SHIFT 3
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-#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
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-#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
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-#define SROM8_FEM_TSSIPOS_MASK 0x0001
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-#define SROM8_FEM_TSSIPOS_SHIFT 0
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-
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-#define SROM8_THERMAL 89
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-
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-/* Temp sense related entries */
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-#define SROM8_MPWR_RAWTS 90
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-#define SROM8_TS_SLP_OPT_CORRX 91
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-/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable,
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- * IQSWP: IQ CAL swap disable */
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-#define SROM8_FOC_HWIQ_IQSWP 92
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-
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-/* Temperature delta for PHY calibration */
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-#define SROM8_PHYCAL_TEMPDELTA 93
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-
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-/* Per-path offsets & fields */
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-#define SROM8_PATH0 96
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-#define SROM8_PATH1 112
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-#define SROM8_PATH2 128
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-#define SROM8_PATH3 144
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-
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-#define SROM8_2G_ITT_MAXP 0
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-#define SROM8_2G_PA 1
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-#define SROM8_5G_ITT_MAXP 4
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-#define SROM8_5GLH_MAXP 5
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-#define SROM8_5G_PA 6
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-#define SROM8_5GL_PA 9
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-#define SROM8_5GH_PA 12
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-
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-/* All the miriad power offsets */
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-#define SROM8_2G_CCKPO 160
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-
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-#define SROM8_2G_OFDMPO 161
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-#define SROM8_5G_OFDMPO 163
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-#define SROM8_5GL_OFDMPO 165
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-#define SROM8_5GH_OFDMPO 167
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-
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-#define SROM8_2G_MCSPO 169
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-#define SROM8_5G_MCSPO 177
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-#define SROM8_5GL_MCSPO 185
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-#define SROM8_5GH_MCSPO 193
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-
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-#define SROM8_CDDPO 201
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-#define SROM8_STBCPO 202
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-#define SROM8_BW40PO 203
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-#define SROM8_BWDUPPO 204
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-
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-/* SISO PA parameters are in the path0 spaces */
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-#define SROM8_SISO 96
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-
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-/* Legacy names for SISO PA paramters */
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-#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
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-#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
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-#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
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-#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
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-#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
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-#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
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-#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
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-#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
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-#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
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-#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
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-#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
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-#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
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-#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
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-#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
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-#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
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-
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-/* SROM REV 9 */
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-#define SROM9_2GPO_CCKBW20 160
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-#define SROM9_2GPO_CCKBW20UL 161
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-#define SROM9_2GPO_LOFDMBW20 162
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-#define SROM9_2GPO_LOFDMBW20UL 164
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-
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-#define SROM9_5GLPO_LOFDMBW20 166
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-#define SROM9_5GLPO_LOFDMBW20UL 168
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-#define SROM9_5GMPO_LOFDMBW20 170
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-#define SROM9_5GMPO_LOFDMBW20UL 172
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-#define SROM9_5GHPO_LOFDMBW20 174
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-#define SROM9_5GHPO_LOFDMBW20UL 176
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-
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-#define SROM9_2GPO_MCSBW20 178
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-#define SROM9_2GPO_MCSBW20UL 180
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-#define SROM9_2GPO_MCSBW40 182
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-
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-#define SROM9_5GLPO_MCSBW20 184
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-#define SROM9_5GLPO_MCSBW20UL 186
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-#define SROM9_5GLPO_MCSBW40 188
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-#define SROM9_5GMPO_MCSBW20 190
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-#define SROM9_5GMPO_MCSBW20UL 192
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-#define SROM9_5GMPO_MCSBW40 194
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-#define SROM9_5GHPO_MCSBW20 196
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-#define SROM9_5GHPO_MCSBW20UL 198
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-#define SROM9_5GHPO_MCSBW40 200
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-
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-#define SROM9_PO_MCS32 202
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-#define SROM9_PO_LOFDM40DUP 203
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-
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-/* SROM flags (see sromvar_t) */
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-
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-/* value continues as described by the next entry */
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-#define SRFL_MORE 1
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-#define SRFL_NOFFS 2 /* value bits can't be all one's */
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-#define SRFL_PRHEX 4 /* value is in hexdecimal format */
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-#define SRFL_PRSIGN 8 /* value is in signed decimal format */
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-#define SRFL_CCODE 0x10 /* value is in country code format */
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-#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
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-#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
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-/* do not generate a nvram param, entry is for mfgc */
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-#define SRFL_NOVAR 0x80
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-
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-/* Max. nvram variable table size */
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-#define MAXSZ_NVRAM_VARS 4096
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-
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-/*
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- * indicates type of value.
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- */
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-enum brcms_srom_var_type {
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- BRCMS_SROM_STRING,
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- BRCMS_SROM_SNUMBER,
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- BRCMS_SROM_UNUMBER
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-};
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-
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-/*
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- * storage type for srom variable.
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- *
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- * var_list: for linked list operations.
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- * varid: identifier of the variable.
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- * var_type: type of variable.
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- * buf: variable value when var_type == BRCMS_SROM_STRING.
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- * uval: unsigned variable value when var_type == BRCMS_SROM_UNUMBER.
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- * sval: signed variable value when var_type == BRCMS_SROM_SNUMBER.
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- */
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-struct brcms_srom_list_head {
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- struct list_head var_list;
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- enum brcms_srom_id varid;
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- enum brcms_srom_var_type var_type;
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- union {
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- char buf[0];
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- u32 uval;
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- s32 sval;
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- };
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-};
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-
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-struct brcms_sromvar {
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- enum brcms_srom_id varid;
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- u32 revmask;
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- u32 flags;
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- u16 off;
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- u16 mask;
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-};
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-
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-struct brcms_varbuf {
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- char *base; /* pointer to buffer base */
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- char *buf; /* pointer to current position */
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- unsigned int size; /* current (residual) size in bytes */
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-};
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-
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-/*
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- * Assumptions:
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- * - Ethernet address spans across 3 consecutive words
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- *
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- * Table rules:
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- * - Add multiple entries next to each other if a value spans across multiple
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- * words (even multiple fields in the same word) with each entry except the
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- * last having it's SRFL_MORE bit set.
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- * - Ethernet address entry does not follow above rule and must not have
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- * SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
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- * - The last entry's name field must be NULL to indicate the end of the table.
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- * Other entries must have non-NULL name.
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- */
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-static const struct brcms_sromvar pci_sromvars[] = {
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- {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
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- 0xffff},
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- {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
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- {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
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- 0xffff},
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- {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
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- {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
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- 0xffff},
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- {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
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- {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
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- {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
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- {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
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- {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
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- {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
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- {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
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- {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
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- {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
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- {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
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- {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
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- {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
|
|
|
- {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
|
|
|
- {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
|
|
|
- {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
|
|
|
- {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
|
|
|
- {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
|
|
|
- {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
|
|
|
- {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
|
|
|
- {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
|
|
|
- {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
|
|
|
- {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
|
|
|
- {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
|
|
|
- {BRCMS_SROM_PA1LOB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
|
|
|
- {BRCMS_SROM_PA1LOB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
|
|
|
- {BRCMS_SROM_PA1LOB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
|
|
|
- {BRCMS_SROM_PA1HIB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
|
|
|
- {BRCMS_SROM_PA1HIB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
|
|
|
- {BRCMS_SROM_PA1HIB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
|
|
|
- {BRCMS_SROM_PA1ITSSIT, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
|
|
|
- {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
|
|
|
- {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
|
|
|
- {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
|
|
|
- {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
|
|
|
- {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
|
|
|
- {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
|
|
|
- {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
|
|
|
- {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
|
|
|
- {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
|
|
|
- {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
|
|
|
- {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
|
|
|
- {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
|
|
|
- {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
|
|
|
- {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
|
|
|
- {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
|
|
|
- {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
|
|
|
- {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
|
|
|
- {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
|
|
|
- SROM4_TXCHAIN_MASK},
|
|
|
- {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
|
|
|
- SROM4_RXCHAIN_MASK},
|
|
|
- {BRCMS_SROM_ANTSWITCH, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
|
|
|
- SROM4_SWITCH_MASK},
|
|
|
- {BRCMS_SROM_TSSIPOS2G, 0xffffff00, 0, SROM8_FEM2G,
|
|
|
- SROM8_FEM_TSSIPOS_MASK},
|
|
|
- {BRCMS_SROM_EXTPAGAIN2G, 0xffffff00, 0, SROM8_FEM2G,
|
|
|
- SROM8_FEM_EXTPA_GAIN_MASK},
|
|
|
- {BRCMS_SROM_PDETRANGE2G, 0xffffff00, 0, SROM8_FEM2G,
|
|
|
- SROM8_FEM_PDET_RANGE_MASK},
|
|
|
- {BRCMS_SROM_TRISO2G, 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
|
|
|
- {BRCMS_SROM_ANTSWCTL2G, 0xffffff00, 0, SROM8_FEM2G,
|
|
|
- SROM8_FEM_ANTSWLUT_MASK},
|
|
|
- {BRCMS_SROM_TSSIPOS5G, 0xffffff00, 0, SROM8_FEM5G,
|
|
|
- SROM8_FEM_TSSIPOS_MASK},
|
|
|
- {BRCMS_SROM_EXTPAGAIN5G, 0xffffff00, 0, SROM8_FEM5G,
|
|
|
- SROM8_FEM_EXTPA_GAIN_MASK},
|
|
|
- {BRCMS_SROM_PDETRANGE5G, 0xffffff00, 0, SROM8_FEM5G,
|
|
|
- SROM8_FEM_PDET_RANGE_MASK},
|
|
|
- {BRCMS_SROM_TRISO5G, 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
|
|
|
- {BRCMS_SROM_ANTSWCTL5G, 0xffffff00, 0, SROM8_FEM5G,
|
|
|
- SROM8_FEM_ANTSWLUT_MASK},
|
|
|
- {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
|
|
|
- {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
|
|
|
-
|
|
|
- {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
|
|
|
- {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
|
|
|
- {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
|
|
|
- 0x01ff},
|
|
|
- {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
|
|
|
- 0xfe00},
|
|
|
- {BRCMS_SROM_TEMPSENSE_SLOPE, 0xffffff00, SRFL_PRHEX,
|
|
|
- SROM8_TS_SLP_OPT_CORRX, 0x00ff},
|
|
|
- {BRCMS_SROM_TEMPCORRX, 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
|
|
|
- 0xfc00},
|
|
|
- {BRCMS_SROM_TEMPSENSE_OPTION, 0xffffff00, SRFL_PRHEX,
|
|
|
- SROM8_TS_SLP_OPT_CORRX, 0x0300},
|
|
|
- {BRCMS_SROM_FREQOFFSET_CORR, 0xffffff00, SRFL_PRHEX,
|
|
|
- SROM8_FOC_HWIQ_IQSWP, 0x000f},
|
|
|
- {BRCMS_SROM_IQCAL_SWP_DIS, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
|
|
|
- 0x0010},
|
|
|
- {BRCMS_SROM_HW_IQCAL_EN, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
|
|
|
- 0x0020},
|
|
|
- {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
|
|
|
- 0x00ff},
|
|
|
-
|
|
|
- {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
|
|
|
- {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_OFDM5GLPO, 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO3, 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO4, 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO5, 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO6, 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
|
|
|
- {BRCMS_SROM_MCS2GPO7, 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO0, 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO1, 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO2, 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO3, 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO4, 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO5, 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO6, 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GPO7, 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO0, 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO1, 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO2, 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO3, 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO4, 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO5, 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO6, 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GLPO7, 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO0, 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO1, 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO2, 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO3, 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO4, 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
|
|
|
- {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
|
|
|
- {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
|
|
|
- {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
|
|
|
- {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
|
|
|
- {BRCMS_SROM_BWDUPPO, 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
|
|
|
-
|
|
|
- /* power per rate from sromrev 9 */
|
|
|
- {BRCMS_SROM_CCKBW202GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
|
|
|
- {BRCMS_SROM_CCKBW20UL2GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW202GPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_2GPO_LOFDMBW20, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW20UL2GPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_2GPO_LOFDMBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW205GLPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GLPO_LOFDMBW20, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GLPO_LOFDMBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW205GMPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GMPO_LOFDMBW20, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GMPO_LOFDMBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW205GHPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GHPO_LOFDMBW20, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDMBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GHPO_LOFDMBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW202GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW20UL2GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW402GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW205GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GLPO_MCSBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW405GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW205GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GMPO_MCSBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW405GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW205GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
|
|
|
- SROM9_5GHPO_MCSBW20UL, 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCSBW405GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
|
|
|
- {BRCMS_SROM_MCS32PO, 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
|
|
|
- {BRCMS_SROM_LEGOFDM40DUPPO, 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
|
|
|
-
|
|
|
- {BRCMS_SROM_NULL, 0, 0, 0, 0}
|
|
|
-};
|
|
|
-
|
|
|
-static const struct brcms_sromvar perpath_pci_sromvars[] = {
|
|
|
- {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
|
|
|
- {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
|
|
|
- {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
|
|
|
- {BRCMS_SROM_PA2GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
|
|
|
- {BRCMS_SROM_PA2GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
|
|
|
- {BRCMS_SROM_PA2GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
|
|
|
- {BRCMS_SROM_MAXP5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
|
|
|
- {BRCMS_SROM_MAXP5GHA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
|
|
|
- {BRCMS_SROM_MAXP5GLA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
|
|
|
- {BRCMS_SROM_PA5GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
|
|
|
- {BRCMS_SROM_PA5GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
|
|
|
- {BRCMS_SROM_PA5GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
|
|
|
- {BRCMS_SROM_PA5GLW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
|
|
|
- {BRCMS_SROM_PA5GLW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_PA5GLW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_PA5GHW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
|
|
|
- {BRCMS_SROM_PA5GHW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_PA5GHW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2,
|
|
|
- 0xffff},
|
|
|
- {BRCMS_SROM_NULL, 0, 0, 0, 0}
|
|
|
-};
|
|
|
-
|
|
|
-/* crc table has the same contents for every device instance, so it can be
|
|
|
- * shared between devices. */
|
|
|
-static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
|
|
|
-
|
|
|
-static uint mask_shift(u16 mask)
|
|
|
-{
|
|
|
- uint i;
|
|
|
- for (i = 0; i < (sizeof(mask) << 3); i++) {
|
|
|
- if (mask & (1 << i))
|
|
|
- return i;
|
|
|
- }
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-static uint mask_width(u16 mask)
|
|
|
-{
|
|
|
- int i;
|
|
|
- for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
|
|
|
- if (mask & (1 << i))
|
|
|
- return (uint) (i - mask_shift(mask) + 1);
|
|
|
- }
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-static inline void le16_to_cpu_buf(u16 *buf, uint nwords)
|
|
|
-{
|
|
|
- while (nwords--)
|
|
|
- *(buf + nwords) = le16_to_cpu(*(__le16 *)(buf + nwords));
|
|
|
-}
|
|
|
-
|
|
|
-static inline void cpu_to_le16_buf(u16 *buf, uint nwords)
|
|
|
-{
|
|
|
- while (nwords--)
|
|
|
- *(__le16 *)(buf + nwords) = cpu_to_le16(*(buf + nwords));
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * convert binary srom data into linked list of srom variable items.
|
|
|
- */
|
|
|
-static int
|
|
|
-_initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
|
|
|
-{
|
|
|
- struct brcms_srom_list_head *entry;
|
|
|
- enum brcms_srom_id id;
|
|
|
- u16 w;
|
|
|
- u32 val = 0;
|
|
|
- const struct brcms_sromvar *srv;
|
|
|
- uint width;
|
|
|
- uint flags;
|
|
|
- u32 sr = (1 << sromrev);
|
|
|
- uint p;
|
|
|
- uint pb = SROM8_PATH0;
|
|
|
- const uint psz = SROM8_PATH1 - SROM8_PATH0;
|
|
|
-
|
|
|
- /* first store the srom revision */
|
|
|
- entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
|
|
|
- if (!entry)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- entry->varid = BRCMS_SROM_REV;
|
|
|
- entry->var_type = BRCMS_SROM_UNUMBER;
|
|
|
- entry->uval = sromrev;
|
|
|
- list_add(&entry->var_list, var_list);
|
|
|
-
|
|
|
- for (srv = pci_sromvars; srv->varid != BRCMS_SROM_NULL; srv++) {
|
|
|
- enum brcms_srom_var_type type;
|
|
|
- u8 ea[ETH_ALEN];
|
|
|
- u8 extra_space = 0;
|
|
|
-
|
|
|
- if ((srv->revmask & sr) == 0)
|
|
|
- continue;
|
|
|
-
|
|
|
- flags = srv->flags;
|
|
|
- id = srv->varid;
|
|
|
-
|
|
|
- /* This entry is for mfgc only. Don't generate param for it, */
|
|
|
- if (flags & SRFL_NOVAR)
|
|
|
- continue;
|
|
|
-
|
|
|
- if (flags & SRFL_ETHADDR) {
|
|
|
- /*
|
|
|
- * stored in string format XX:XX:XX:XX:XX:XX (17 chars)
|
|
|
- */
|
|
|
- ea[0] = (srom[srv->off] >> 8) & 0xff;
|
|
|
- ea[1] = srom[srv->off] & 0xff;
|
|
|
- ea[2] = (srom[srv->off + 1] >> 8) & 0xff;
|
|
|
- ea[3] = srom[srv->off + 1] & 0xff;
|
|
|
- ea[4] = (srom[srv->off + 2] >> 8) & 0xff;
|
|
|
- ea[5] = srom[srv->off + 2] & 0xff;
|
|
|
- /* 17 characters + string terminator - union size */
|
|
|
- extra_space = 18 - sizeof(s32);
|
|
|
- type = BRCMS_SROM_STRING;
|
|
|
- } else {
|
|
|
- w = srom[srv->off];
|
|
|
- val = (w & srv->mask) >> mask_shift(srv->mask);
|
|
|
- width = mask_width(srv->mask);
|
|
|
-
|
|
|
- while (srv->flags & SRFL_MORE) {
|
|
|
- srv++;
|
|
|
- if (srv->off == 0)
|
|
|
- continue;
|
|
|
-
|
|
|
- w = srom[srv->off];
|
|
|
- val +=
|
|
|
- ((w & srv->mask) >> mask_shift(srv->
|
|
|
- mask)) <<
|
|
|
- width;
|
|
|
- width += mask_width(srv->mask);
|
|
|
- }
|
|
|
-
|
|
|
- if ((flags & SRFL_NOFFS)
|
|
|
- && ((int)val == (1 << width) - 1))
|
|
|
- continue;
|
|
|
-
|
|
|
- if (flags & SRFL_CCODE) {
|
|
|
- type = BRCMS_SROM_STRING;
|
|
|
- } else if (flags & SRFL_LEDDC) {
|
|
|
- /* LED Powersave duty cycle has to be scaled:
|
|
|
- *(oncount >> 24) (offcount >> 8)
|
|
|
- */
|
|
|
- u32 w32 = /* oncount */
|
|
|
- (((val >> 8) & 0xff) << 24) |
|
|
|
- /* offcount */
|
|
|
- (((val & 0xff)) << 8);
|
|
|
- type = BRCMS_SROM_UNUMBER;
|
|
|
- val = w32;
|
|
|
- } else if ((flags & SRFL_PRSIGN)
|
|
|
- && (val & (1 << (width - 1)))) {
|
|
|
- type = BRCMS_SROM_SNUMBER;
|
|
|
- val |= ~0 << width;
|
|
|
- } else
|
|
|
- type = BRCMS_SROM_UNUMBER;
|
|
|
- }
|
|
|
-
|
|
|
- entry = kzalloc(sizeof(struct brcms_srom_list_head) +
|
|
|
- extra_space, GFP_KERNEL);
|
|
|
- if (!entry)
|
|
|
- return -ENOMEM;
|
|
|
- entry->varid = id;
|
|
|
- entry->var_type = type;
|
|
|
- if (flags & SRFL_ETHADDR) {
|
|
|
- snprintf(entry->buf, 18, "%pM", ea);
|
|
|
- } else if (flags & SRFL_CCODE) {
|
|
|
- if (val == 0)
|
|
|
- entry->buf[0] = '\0';
|
|
|
- else
|
|
|
- snprintf(entry->buf, 3, "%c%c",
|
|
|
- (val >> 8), (val & 0xff));
|
|
|
- } else {
|
|
|
- entry->uval = val;
|
|
|
- }
|
|
|
-
|
|
|
- list_add(&entry->var_list, var_list);
|
|
|
- }
|
|
|
-
|
|
|
- for (p = 0; p < MAX_PATH_SROM; p++) {
|
|
|
- for (srv = perpath_pci_sromvars;
|
|
|
- srv->varid != BRCMS_SROM_NULL; srv++) {
|
|
|
- if ((srv->revmask & sr) == 0)
|
|
|
- continue;
|
|
|
-
|
|
|
- if (srv->flags & SRFL_NOVAR)
|
|
|
- continue;
|
|
|
-
|
|
|
- w = srom[pb + srv->off];
|
|
|
- val = (w & srv->mask) >> mask_shift(srv->mask);
|
|
|
- width = mask_width(srv->mask);
|
|
|
-
|
|
|
- /* Cheating: no per-path var is more than
|
|
|
- * 1 word */
|
|
|
- if ((srv->flags & SRFL_NOFFS)
|
|
|
- && ((int)val == (1 << width) - 1))
|
|
|
- continue;
|
|
|
-
|
|
|
- entry =
|
|
|
- kzalloc(sizeof(struct brcms_srom_list_head),
|
|
|
- GFP_KERNEL);
|
|
|
- if (!entry)
|
|
|
- return -ENOMEM;
|
|
|
- entry->varid = srv->varid+p;
|
|
|
- entry->var_type = BRCMS_SROM_UNUMBER;
|
|
|
- entry->uval = val;
|
|
|
- list_add(&entry->var_list, var_list);
|
|
|
- }
|
|
|
- pb += psz;
|
|
|
- }
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * The crc check is done on a little-endian array, we need
|
|
|
- * to switch the bytes around before checking crc (and
|
|
|
- * then switch it back).
|
|
|
- */
|
|
|
-static int do_crc_check(u16 *buf, unsigned nwords)
|
|
|
-{
|
|
|
- u8 crc;
|
|
|
-
|
|
|
- cpu_to_le16_buf(buf, nwords);
|
|
|
- crc = crc8(brcms_srom_crc8_table, (void *)buf, nwords << 1, CRC8_INIT_VALUE);
|
|
|
- le16_to_cpu_buf(buf, nwords);
|
|
|
-
|
|
|
- return crc == CRC8_GOOD_VALUE(brcms_srom_crc8_table);
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * Read in and validate sprom.
|
|
|
- * Return 0 on success, nonzero on error.
|
|
|
- */
|
|
|
-static int
|
|
|
-sprom_read_pci(struct si_pub *sih, u16 *buf, uint nwords, bool check_crc)
|
|
|
-{
|
|
|
- int err = 0;
|
|
|
- uint i;
|
|
|
- struct bcma_device *core;
|
|
|
- uint sprom_offset;
|
|
|
-
|
|
|
- /* determine core to read */
|
|
|
- if (ai_get_ccrev(sih) < 32) {
|
|
|
- core = ai_findcore(sih, BCMA_CORE_80211, 0);
|
|
|
- sprom_offset = PCI_BAR0_SPROM_OFFSET;
|
|
|
- } else {
|
|
|
- core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
|
|
|
- sprom_offset = CHIPCREGOFFS(sromotp);
|
|
|
- }
|
|
|
-
|
|
|
- /* read the sprom */
|
|
|
- for (i = 0; i < nwords; i++)
|
|
|
- buf[i] = bcma_read16(core, sprom_offset+i*2);
|
|
|
-
|
|
|
- if (buf[0] == 0xffff)
|
|
|
- /*
|
|
|
- * The hardware thinks that an srom that starts with
|
|
|
- * 0xffff is blank, regardless of the rest of the
|
|
|
- * content, so declare it bad.
|
|
|
- */
|
|
|
- return -ENODATA;
|
|
|
-
|
|
|
- if (check_crc && !do_crc_check(buf, nwords))
|
|
|
- err = -EIO;
|
|
|
-
|
|
|
- return err;
|
|
|
-}
|
|
|
-
|
|
|
-static int otp_read_pci(struct si_pub *sih, u16 *buf, uint nwords)
|
|
|
-{
|
|
|
- u8 *otp;
|
|
|
- uint sz = OTP_SZ_MAX / 2; /* size in words */
|
|
|
- int err = 0;
|
|
|
-
|
|
|
- otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
|
|
|
- if (otp == NULL)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
|
|
|
-
|
|
|
- sz = min_t(uint, sz, nwords);
|
|
|
- memcpy(buf, otp, sz * 2);
|
|
|
-
|
|
|
- kfree(otp);
|
|
|
-
|
|
|
- /* Check CRC */
|
|
|
- if (buf[0] == 0xffff)
|
|
|
- /* The hardware thinks that an srom that starts with 0xffff
|
|
|
- * is blank, regardless of the rest of the content, so declare
|
|
|
- * it bad.
|
|
|
- */
|
|
|
- return -ENODATA;
|
|
|
-
|
|
|
- /* fixup the endianness so crc8 will pass */
|
|
|
- cpu_to_le16_buf(buf, sz);
|
|
|
- if (crc8(brcms_srom_crc8_table, (u8 *) buf, sz * 2,
|
|
|
- CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table))
|
|
|
- err = -EIO;
|
|
|
- else
|
|
|
- /* now correct the endianness of the byte array */
|
|
|
- le16_to_cpu_buf(buf, sz);
|
|
|
-
|
|
|
- return err;
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * Initialize nonvolatile variable table from sprom.
|
|
|
- * Return 0 on success, nonzero on error.
|
|
|
- */
|
|
|
-int srom_var_init(struct si_pub *sih)
|
|
|
-{
|
|
|
- u16 *srom;
|
|
|
- u8 sromrev = 0;
|
|
|
- u32 sr;
|
|
|
- int err = 0;
|
|
|
-
|
|
|
- /*
|
|
|
- * Apply CRC over SROM content regardless SROM is present or not.
|
|
|
- */
|
|
|
- srom = kmalloc(SROM_MAX, GFP_ATOMIC);
|
|
|
- if (!srom)
|
|
|
- return -ENOMEM;
|
|
|
-
|
|
|
- crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY);
|
|
|
- if (ai_is_sprom_available(sih)) {
|
|
|
- err = sprom_read_pci(sih, srom, SROM4_WORDS, true);
|
|
|
-
|
|
|
- if (err == 0)
|
|
|
- /* srom read and passed crc */
|
|
|
- /* top word of sprom contains version and crc8 */
|
|
|
- sromrev = srom[SROM4_CRCREV] & 0xff;
|
|
|
- } else {
|
|
|
- /* Use OTP if SPROM not available */
|
|
|
- err = otp_read_pci(sih, srom, SROM4_WORDS);
|
|
|
- if (err == 0)
|
|
|
- /* OTP only contain SROM rev8/rev9 for now */
|
|
|
- sromrev = srom[SROM4_CRCREV] & 0xff;
|
|
|
- }
|
|
|
-
|
|
|
- if (!err) {
|
|
|
- struct si_info *sii = (struct si_info *)sih;
|
|
|
-
|
|
|
- /* Bitmask for the sromrev */
|
|
|
- sr = 1 << sromrev;
|
|
|
-
|
|
|
- /*
|
|
|
- * srom version check: Current valid versions: 8, 9
|
|
|
- */
|
|
|
- if ((sr & 0x300) == 0) {
|
|
|
- err = -EINVAL;
|
|
|
- goto errout;
|
|
|
- }
|
|
|
-
|
|
|
- INIT_LIST_HEAD(&sii->var_list);
|
|
|
-
|
|
|
- /* parse SROM into name=value pairs. */
|
|
|
- err = _initvars_srom_pci(sromrev, srom, &sii->var_list);
|
|
|
- if (err)
|
|
|
- srom_free_vars(sih);
|
|
|
- }
|
|
|
-
|
|
|
-errout:
|
|
|
- kfree(srom);
|
|
|
- return err;
|
|
|
-}
|
|
|
-
|
|
|
-void srom_free_vars(struct si_pub *sih)
|
|
|
-{
|
|
|
- struct si_info *sii;
|
|
|
- struct brcms_srom_list_head *entry, *next;
|
|
|
-
|
|
|
- sii = (struct si_info *)sih;
|
|
|
- list_for_each_entry_safe(entry, next, &sii->var_list, var_list) {
|
|
|
- list_del(&entry->var_list);
|
|
|
- kfree(entry);
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * Search the name=value vars for a specific one and return its value.
|
|
|
- * Returns NULL if not found.
|
|
|
- */
|
|
|
-char *getvar(struct si_pub *sih, enum brcms_srom_id id)
|
|
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-{
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- struct si_info *sii;
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- struct brcms_srom_list_head *entry;
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-
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- sii = (struct si_info *)sih;
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-
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- list_for_each_entry(entry, &sii->var_list, var_list)
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- if (entry->varid == id)
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- return &entry->buf[0];
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-
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- /* nothing found */
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- return NULL;
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-}
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-
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-/*
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- * Search the vars for a specific one and return its value as
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- * an integer. Returns 0 if not found.-
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- */
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-int getintvar(struct si_pub *sih, enum brcms_srom_id id)
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-{
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- struct si_info *sii;
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- struct brcms_srom_list_head *entry;
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- unsigned long res;
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-
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- sii = (struct si_info *)sih;
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-
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- list_for_each_entry(entry, &sii->var_list, var_list)
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- if (entry->varid == id) {
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- if (entry->var_type == BRCMS_SROM_SNUMBER ||
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- entry->var_type == BRCMS_SROM_UNUMBER)
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- return (int)entry->sval;
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- else if (!kstrtoul(&entry->buf[0], 0, &res))
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- return (int)res;
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- }
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-
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- return 0;
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-}
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Hauke Mehrtens