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@@ -48,7 +48,7 @@
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#define OMAP_TIMER_COUNTER_REG 0x28
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#define OMAP_TIMER_COUNTER_REG 0x28
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#define OMAP_TIMER_LOAD_REG 0x2c
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#define OMAP_TIMER_LOAD_REG 0x2c
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#define OMAP_TIMER_TRIGGER_REG 0x30
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#define OMAP_TIMER_TRIGGER_REG 0x30
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-#define OMAP_TIMER_WRITE_PEND_REG 0x34
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+#define OMAP_TIMER_WRITE_PEND_REG 0x34
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#define OMAP_TIMER_MATCH_REG 0x38
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#define OMAP_TIMER_MATCH_REG 0x38
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#define OMAP_TIMER_CAPTURE_REG 0x3c
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#define OMAP_TIMER_CAPTURE_REG 0x3c
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#define OMAP_TIMER_IF_CTRL_REG 0x40
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#define OMAP_TIMER_IF_CTRL_REG 0x40
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@@ -82,8 +82,11 @@ struct omap_dm_timer {
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#define omap_dm_clk_enable(x)
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#define omap_dm_clk_enable(x)
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#define omap_dm_clk_disable(x)
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#define omap_dm_clk_disable(x)
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+#define omap2_dm_timers NULL
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+#define omap2_dm_source_names NULL
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+#define omap2_dm_source_clocks NULL
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-static struct omap_dm_timer dm_timers[] = {
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+static struct omap_dm_timer omap1_dm_timers[] = {
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{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
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{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
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{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
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{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
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{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
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{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
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@@ -94,12 +97,15 @@ static struct omap_dm_timer dm_timers[] = {
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{ .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
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{ .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
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};
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};
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+static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
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+
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#elif defined(CONFIG_ARCH_OMAP2)
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#elif defined(CONFIG_ARCH_OMAP2)
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-#define omap_dm_clk_enable(x) clk_enable(x)
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-#define omap_dm_clk_disable(x) clk_disable(x)
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+#define omap_dm_clk_enable(x) clk_enable(x)
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+#define omap_dm_clk_disable(x) clk_disable(x)
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+#define omap1_dm_timers NULL
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-static struct omap_dm_timer dm_timers[] = {
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+static struct omap_dm_timer omap2_dm_timers[] = {
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{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
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{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
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{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
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{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
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{ .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
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{ .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
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@@ -114,13 +120,15 @@ static struct omap_dm_timer dm_timers[] = {
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{ .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
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{ .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
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};
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};
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-static const char *dm_source_names[] = {
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+static const char *omap2_dm_source_names[] __initdata = {
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"sys_ck",
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"sys_ck",
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"func_32k_ck",
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"func_32k_ck",
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- "alt_ck"
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+ "alt_ck",
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+ NULL
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};
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};
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-static struct clk *dm_source_clocks[3];
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+static struct clk **omap2_dm_source_clocks[3];
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+static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
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#else
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#else
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@@ -128,7 +136,10 @@ static struct clk *dm_source_clocks[3];
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#endif
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#endif
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-static const int dm_timer_count = ARRAY_SIZE(dm_timers);
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+static struct omap_dm_timer *dm_timers;
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+static char **dm_source_names;
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+static struct clk **dm_source_clocks;
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+
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static spinlock_t dm_timer_lock;
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static spinlock_t dm_timer_lock;
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
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@@ -486,7 +497,7 @@ int omap_dm_timers_active(void)
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return 0;
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return 0;
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}
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}
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-int omap_dm_timer_init(void)
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+int __init omap_dm_timer_init(void)
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{
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{
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struct omap_dm_timer *timer;
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struct omap_dm_timer *timer;
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int i;
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int i;
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@@ -495,27 +506,33 @@ int omap_dm_timer_init(void)
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return -ENODEV;
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return -ENODEV;
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spin_lock_init(&dm_timer_lock);
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spin_lock_init(&dm_timer_lock);
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-#ifdef CONFIG_ARCH_OMAP2
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- for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
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- dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
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- BUG_ON(dm_source_clocks[i] == NULL);
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+
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+ if (cpu_class_is_omap1())
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+ dm_timers = omap1_dm_timers;
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+ else if (cpu_is_omap24xx()) {
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+ dm_timers = omap2_dm_timers;
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+ dm_source_names = (char **)omap2_dm_source_names;
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+ dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
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}
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}
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-#endif
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+
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+ if (cpu_class_is_omap2())
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+ for (i = 0; dm_source_names[i] != NULL; i++)
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+ dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
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+
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if (cpu_is_omap243x())
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if (cpu_is_omap243x())
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dm_timers[0].phys_base = 0x49018000;
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dm_timers[0].phys_base = 0x49018000;
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for (i = 0; i < dm_timer_count; i++) {
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for (i = 0; i < dm_timer_count; i++) {
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-#ifdef CONFIG_ARCH_OMAP2
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- char clk_name[16];
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-#endif
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-
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timer = &dm_timers[i];
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timer = &dm_timers[i];
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- timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
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+ timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
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#ifdef CONFIG_ARCH_OMAP2
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#ifdef CONFIG_ARCH_OMAP2
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- sprintf(clk_name, "gpt%d_ick", i + 1);
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- timer->iclk = clk_get(NULL, clk_name);
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- sprintf(clk_name, "gpt%d_fck", i + 1);
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- timer->fclk = clk_get(NULL, clk_name);
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+ if (cpu_class_is_omap2()) {
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+ char clk_name[16];
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+ sprintf(clk_name, "gpt%d_ick", i + 1);
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+ timer->iclk = clk_get(NULL, clk_name);
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+ sprintf(clk_name, "gpt%d_fck", i + 1);
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+ timer->fclk = clk_get(NULL, clk_name);
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+ }
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#endif
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#endif
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}
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}
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