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@@ -595,6 +595,7 @@ void scic_sds_controller_enable_port_task_scheduler(
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*/
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void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
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{
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+ const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
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u32 afe_status;
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u32 phy_id;
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@@ -632,6 +633,8 @@ void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
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}
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for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
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+ const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
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+
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if (is_b0()) {
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/* Configure transmitter SSC parameters */
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scu_afe_txreg_write(scic, phy_id, afe_tx_ssc_control, 0x00030000);
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@@ -691,16 +694,16 @@ void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
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}
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udelay(AFE_REGISTER_WRITE_DELAY);
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- scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, 0x000E7C03);
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+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control0);
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udelay(AFE_REGISTER_WRITE_DELAY);
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- scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control1, 0x000E7C03);
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+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control1);
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udelay(AFE_REGISTER_WRITE_DELAY);
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- scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control2, 0x000E7C03);
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+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control2);
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udelay(AFE_REGISTER_WRITE_DELAY);
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- scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control3, 0x000E7C03);
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+ scu_afe_txreg_write(scic, phy_id, afe_tx_amp_control0, oem_phy->afe_tx_amp_control3);
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udelay(AFE_REGISTER_WRITE_DELAY);
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}
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@@ -2027,6 +2030,7 @@ void scic_sds_controller_release_frame(
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*/
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static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic)
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{
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+ struct isci_host *ihost = sci_object_get_association(scic);
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u16 index;
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/* Default to APC mode. */
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@@ -2058,7 +2062,7 @@ static void scic_sds_controller_set_default_config_parameters(struct scic_sds_co
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* is worked around by having the upper 32-bits of SAS address
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* with a value greater then the Vitesse company identifier.
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* Hence, usage of 0x5FCFFFFF. */
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- scic->oem_parameters.sds1.phys[index].sas_address.low = 0x00000001;
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+ scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id;
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scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
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}
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@@ -2604,14 +2608,11 @@ enum sci_status scic_oem_parameters_set(
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struct scic_sds_controller *scic,
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union scic_oem_parameters *scic_parms)
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{
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- if (
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- (scic->parent.state_machine.current_state_id
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- == SCI_BASE_CONTROLLER_STATE_RESET)
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- || (scic->parent.state_machine.current_state_id
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- == SCI_BASE_CONTROLLER_STATE_INITIALIZING)
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- || (scic->parent.state_machine.current_state_id
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- == SCI_BASE_CONTROLLER_STATE_INITIALIZED)
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- ) {
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+ u32 state = scic->parent.state_machine.current_state_id;
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+
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+ if (state == SCI_BASE_CONTROLLER_STATE_RESET ||
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+ state == SCI_BASE_CONTROLLER_STATE_INITIALIZING ||
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+ state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) {
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u16 index;
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u8 combined_phy_mask = 0;
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@@ -2651,7 +2652,8 @@ enum sci_status scic_oem_parameters_set(
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if (scic_parms->sds1.controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT)
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return SCI_FAILURE_INVALID_PARAMETER_VALUE;
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- memcpy(&scic->oem_parameters, scic_parms, sizeof(*scic_parms));
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+ scic->oem_parameters.sds1 = scic_parms->sds1;
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+
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return SCI_SUCCESS;
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}
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