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@@ -19,6 +19,7 @@
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/module.h>
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+#include <asm/oprofile_impl.h>
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#include <asm/cputable.h>
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#include <asm/cputable.h>
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struct cpu_spec* cur_cpu_spec = NULL;
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struct cpu_spec* cur_cpu_spec = NULL;
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@@ -54,24 +55,32 @@ struct cpu_spec cpu_specs[] = {
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.pvr_value = 0x00400000,
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.pvr_value = 0x00400000,
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.cpu_name = "POWER3 (630)",
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.cpu_name = "POWER3 (630)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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- CPU_FTR_PMC8,
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+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power3,
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.cpu_setup = __setup_cpu_power3,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/power3",
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+ .oprofile_model = &op_model_rs64,
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+#endif
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},
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},
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{ /* Power3+ */
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{ /* Power3+ */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00410000,
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.pvr_value = 0x00410000,
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.cpu_name = "POWER3 (630+)",
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.cpu_name = "POWER3 (630+)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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- CPU_FTR_PMC8,
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+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power3,
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.cpu_setup = __setup_cpu_power3,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/power3",
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+ .oprofile_model = &op_model_rs64,
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+#endif
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},
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},
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{ /* Northstar */
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{ /* Northstar */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -79,11 +88,16 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-II (northstar)",
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.cpu_name = "RS64-II (northstar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power3,
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.cpu_setup = __setup_cpu_power3,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/rs64",
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+ .oprofile_model = &op_model_rs64,
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+#endif
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},
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},
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{ /* Pulsar */
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{ /* Pulsar */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -91,11 +105,16 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-III (pulsar)",
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.cpu_name = "RS64-III (pulsar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power3,
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.cpu_setup = __setup_cpu_power3,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/rs64",
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+ .oprofile_model = &op_model_rs64,
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+#endif
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},
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},
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{ /* I-star */
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{ /* I-star */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -103,11 +122,16 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-III (icestar)",
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.cpu_name = "RS64-III (icestar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power3,
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.cpu_setup = __setup_cpu_power3,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/rs64",
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+ .oprofile_model = &op_model_rs64,
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+#endif
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},
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},
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{ /* S-star */
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{ /* S-star */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -115,11 +139,16 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "RS64-IV (sstar)",
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.cpu_name = "RS64-IV (sstar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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- CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
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+ CPU_FTR_MMCRA | CPU_FTR_CTRL,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power3,
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.cpu_setup = __setup_cpu_power3,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/rs64",
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+ .oprofile_model = &op_model_rs64,
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+#endif
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},
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},
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{ /* Power4 */
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{ /* Power4 */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -127,11 +156,16 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "POWER4 (gp)",
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.cpu_name = "POWER4 (gp)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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+ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power4,
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.cpu_setup = __setup_cpu_power4,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/power4",
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+ .oprofile_model = &op_model_rs64,
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+#endif
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},
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},
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{ /* Power4+ */
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{ /* Power4+ */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -139,11 +173,16 @@ struct cpu_spec cpu_specs[] = {
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.cpu_name = "POWER4+ (gq)",
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.cpu_name = "POWER4+ (gq)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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- CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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+ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_power4,
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.cpu_setup = __setup_cpu_power4,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/power4",
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+ .oprofile_model = &op_model_power4,
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+#endif
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},
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},
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{ /* PPC970 */
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{ /* PPC970 */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -152,12 +191,17 @@ struct cpu_spec cpu_specs[] = {
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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- CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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+ CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
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.cpu_user_features = COMMON_USER_PPC64 |
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_ppc970,
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.cpu_setup = __setup_cpu_ppc970,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/970",
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+ .oprofile_model = &op_model_power4,
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+#endif
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},
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},
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{ /* PPC970FX */
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{ /* PPC970FX */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -166,12 +210,17 @@ struct cpu_spec cpu_specs[] = {
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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- CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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+ CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
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.cpu_user_features = COMMON_USER_PPC64 |
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 8,
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.cpu_setup = __setup_cpu_ppc970,
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.cpu_setup = __setup_cpu_ppc970,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/970",
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+ .oprofile_model = &op_model_power4,
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+#endif
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},
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},
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{ /* PPC970MP */
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{ /* PPC970MP */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -180,12 +229,16 @@ struct cpu_spec cpu_specs[] = {
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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- CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
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+ CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
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.cpu_user_features = COMMON_USER_PPC64 |
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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.cpu_setup = __setup_cpu_ppc970,
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.cpu_setup = __setup_cpu_ppc970,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/970",
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+ .oprofile_model = &op_model_power4,
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+#endif
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},
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},
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{ /* Power5 */
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{ /* Power5 */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -199,7 +252,12 @@ struct cpu_spec cpu_specs[] = {
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 6,
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.cpu_setup = __setup_cpu_power4,
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.cpu_setup = __setup_cpu_power4,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/power5",
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+ .oprofile_model = &op_model_power4,
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+#endif
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},
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},
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{ /* Power5 */
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{ /* Power5 */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -213,7 +271,12 @@ struct cpu_spec cpu_specs[] = {
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 6,
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.cpu_setup = __setup_cpu_power4,
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.cpu_setup = __setup_cpu_power4,
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+#ifdef CONFIG_OPROFILE
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+ .oprofile_cpu_type = "ppc64/power5",
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+ .oprofile_model = &op_model_power4,
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+#endif
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},
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},
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{ /* BE DD1.x */
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{ /* BE DD1.x */
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.pvr_mask = 0xffff0000,
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.pvr_mask = 0xffff0000,
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@@ -239,6 +302,7 @@ struct cpu_spec cpu_specs[] = {
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.cpu_user_features = COMMON_USER_PPC64,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.dcache_bsize = 128,
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+ .num_pmcs = 6,
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.cpu_setup = __setup_cpu_power4,
|
|
.cpu_setup = __setup_cpu_power4,
|
|
}
|
|
}
|
|
};
|
|
};
|