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@@ -388,11 +388,7 @@ static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
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*
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* Output : number of served packets
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*/
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-#ifdef MV643XX_NAPI
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static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
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-#else
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-static int mv643xx_eth_receive_queue(struct net_device *dev)
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-#endif
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{
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struct mv643xx_private *mp = netdev_priv(dev);
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struct net_device_stats *stats = &mp->stats;
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@@ -400,15 +396,14 @@ static int mv643xx_eth_receive_queue(struct net_device *dev)
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struct sk_buff *skb;
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struct pkt_info pkt_info;
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-#ifdef MV643XX_NAPI
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while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
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-#else
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- while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
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-#endif
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mp->rx_desc_count--;
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received_packets++;
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- /* Update statistics. Note byte count includes 4 byte CRC count */
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+ /*
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+ * Update statistics.
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+ * Note byte count includes 4 byte CRC count
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+ */
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stats->rx_packets++;
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stats->rx_bytes += pkt_info.byte_cnt;
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skb = pkt_info.return_info;
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@@ -532,48 +527,10 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
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/* Read interrupt cause registers */
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eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
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ETH_INT_UNMASK_ALL;
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-
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- if (eth_int_cause & BIT1)
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+ if (eth_int_cause & ETH_INT_CAUSE_EXT) {
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eth_int_cause_ext = mv_read(
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MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
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ETH_INT_UNMASK_ALL_EXT;
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-
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-#ifdef MV643XX_NAPI
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- if (!(eth_int_cause & 0x0007fffd)) {
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- /* Dont ack the Rx interrupt */
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-#endif
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- /*
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- * Clear specific ethernet port intrerrupt registers by
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- * acknowleding relevant bits.
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- */
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- mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
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- ~eth_int_cause);
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- if (eth_int_cause_ext != 0x0) {
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- mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
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- (port_num), ~eth_int_cause_ext);
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- /* UDP change : We may need this */
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- if (eth_int_cause_ext & (BIT0 | BIT8))
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- mv643xx_eth_free_completed_tx_descs(dev);
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- }
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-#ifdef MV643XX_NAPI
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- } else {
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- if (netif_rx_schedule_prep(dev)) {
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- /* Mask all the interrupts */
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- mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
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- ETH_INT_MASK_ALL);
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- /* wait for previous write to complete */
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- mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
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- __netif_rx_schedule(dev);
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- }
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-#else
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- if (eth_int_cause & (BIT2 | BIT11))
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- mv643xx_eth_receive_queue(dev, 0);
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-
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- /*
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- * After forwarded received packets to upper layer, add a task
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- * in an interrupts enabled context that refills the RX ring
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- * with skb's.
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- */
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#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
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/* Mask all interrupts on ethernet port */
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mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
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@@ -586,11 +543,12 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
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#else
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mp->rx_task.func(dev);
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#endif
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-#endif
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+ mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
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+ ~eth_int_cause_ext);
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}
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/* PHY status changed */
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- if (eth_int_cause_ext & (BIT16 | BIT20)) {
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+ if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) {
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struct ethtool_cmd cmd;
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if (mii_link_ok(&mp->mii)) {
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@@ -610,6 +568,23 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
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}
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}
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+#ifdef MV643XX_NAPI
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+ if (eth_int_cause & ETH_INT_CAUSE_RX) {
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+ /* schedule the NAPI poll routine to maintain port */
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+ mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
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+ ETH_INT_MASK_ALL);
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+ /* wait for previous write to complete */
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+ mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
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+
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+ netif_rx_schedule(dev);
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+ }
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+#else
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+ if (eth_int_cause & ETH_INT_CAUSE_RX)
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+ mv643xx_eth_receive_queue(dev, INT_MAX);
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+ if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
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+ mv643xx_eth_free_completed_tx_descs(dev);
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+#endif
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+
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/*
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* If no real interrupt occured, exit.
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* This can happen when using gigE interrupt coalescing mechanism.
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