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@@ -33,8 +33,12 @@
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#include "omap4-sar-layout.h"
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#include "common.h"
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-#define MAX_NR_REG_BANKS 5
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-#define MAX_IRQS 160
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+#define AM43XX_NR_REG_BANKS 7
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+#define AM43XX_IRQS 224
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+#define MAX_NR_REG_BANKS AM43XX_NR_REG_BANKS
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+#define MAX_IRQS AM43XX_IRQS
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+#define DEFAULT_NR_REG_BANKS 5
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+#define DEFAULT_IRQS 160
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#define WKG_MASK_ALL 0x00000000
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#define WKG_UNMASK_ALL 0xffffffff
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#define CPU_ENA_OFFSET 0x400
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@@ -47,8 +51,8 @@ static void __iomem *wakeupgen_base;
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static void __iomem *sar_base;
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static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
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static unsigned int irq_target_cpu[MAX_IRQS];
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-static unsigned int irq_banks = MAX_NR_REG_BANKS;
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-static unsigned int max_irqs = MAX_IRQS;
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+static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
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+static unsigned int max_irqs = DEFAULT_IRQS;
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static unsigned int omap_secure_apis;
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/*
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@@ -418,12 +422,16 @@ int __init omap_wakeupgen_init(void)
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irq_banks = OMAP4_NR_BANKS;
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max_irqs = OMAP4_NR_IRQS;
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omap_secure_apis = 1;
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+ } else if (soc_is_am43xx()) {
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+ irq_banks = AM43XX_NR_REG_BANKS;
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+ max_irqs = AM43XX_IRQS;
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}
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/* Clear all IRQ bitmasks at wakeupGen level */
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for (i = 0; i < irq_banks; i++) {
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wakeupgen_writel(0, i, CPU0_ID);
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- wakeupgen_writel(0, i, CPU1_ID);
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+ if (!soc_is_am43xx())
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+ wakeupgen_writel(0, i, CPU1_ID);
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}
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/*
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