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@@ -58,8 +58,6 @@
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#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
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#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
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-#define OMAP_HDMI_TIMINGS_NB 34
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-
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#define HDMI_DEFAULT_REGN 16
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#define HDMI_DEFAULT_REGM2 1
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@@ -88,7 +86,7 @@ static struct {
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* map it to corresponding CEA or VESA index.
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*/
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-static const struct hdmi_config cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
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+static const struct hdmi_config cea_timings[] = {
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{ {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI} },
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{ {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI} },
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{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI} },
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@@ -104,6 +102,8 @@ static const struct hdmi_config cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
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{ {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI} },
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{ {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI} },
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{ {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI} },
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+};
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+static const struct hdmi_config vesa_timings[] = {
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/* VESA From Here */
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{ {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI} },
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{ {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI} },
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@@ -126,39 +126,6 @@ static const struct hdmi_config cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
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{ {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI} }
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};
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-/*
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- * This is a static mapping array which maps the timing values
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- * with corresponding CEA / VESA code
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- */
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-static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
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- 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
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- /* <--15 CEA 17--> vesa*/
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- 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
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- 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
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-};
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-
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-/*
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- * This is reverse static mapping which maps the CEA / VESA code
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- * to the corresponding timing values
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- */
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-static const int code_cea[39] = {
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- -1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
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- -1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
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- 7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
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- 11, 12, 14, -1, -1, 13, 13, 4, 4
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-};
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-
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-static const int code_vesa[85] = {
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- -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
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- -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
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- -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
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- -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
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- -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
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- -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
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- -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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- -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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- -1, 27, 28, -1, 33};
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-
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static int hdmi_runtime_get(void)
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{
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int r;
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@@ -188,82 +155,83 @@ int hdmi_init_display(struct omap_dss_device *dssdev)
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return 0;
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}
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-static int get_timings_index(void)
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+static const struct hdmi_config *hdmi_find_timing(
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+ const struct hdmi_config *timings_arr,
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+ int len)
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{
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- int code;
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+ int i;
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- if (hdmi.mode == 0)
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- code = code_vesa[hdmi.code];
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- else
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- code = code_cea[hdmi.code];
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+ for (i = 0; i < len; i++) {
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+ if (timings_arr[i].cm.code == hdmi.code)
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+ return &timings_arr[i];
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+ }
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+ return NULL;
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+}
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- if (code == -1) {
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- /* HDMI code 4 corresponds to 640 * 480 VGA */
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- hdmi.code = 4;
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- /* DVI mode 1 corresponds to HDMI 0 to DVI */
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- hdmi.mode = HDMI_DVI;
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+static const struct hdmi_config *hdmi_get_timings(void)
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+{
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+ const struct hdmi_config *arr;
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+ int len;
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+
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+ if (hdmi.mode == HDMI_DVI) {
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+ arr = vesa_timings;
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+ len = ARRAY_SIZE(vesa_timings);
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+ } else {
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+ arr = cea_timings;
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+ len = ARRAY_SIZE(cea_timings);
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+ }
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+
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+ return hdmi_find_timing(arr, len);
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+}
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+
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+static bool hdmi_timings_compare(struct omap_video_timings *timing1,
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+ const struct hdmi_video_timings *timing2)
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+{
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+ int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
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+
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+ if ((timing2->pixel_clock == timing1->pixel_clock) &&
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+ (timing2->x_res == timing1->x_res) &&
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+ (timing2->y_res == timing1->y_res)) {
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+
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+ timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
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+ timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
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+ timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
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+ timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
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- code = code_vesa[hdmi.code];
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+ DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
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+ "timing2_hsync = %d timing2_vsync = %d\n",
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+ timing1_hsync, timing1_vsync,
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+ timing2_hsync, timing2_vsync);
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+
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+ if ((timing1_hsync == timing2_hsync) &&
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+ (timing1_vsync == timing2_vsync)) {
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+ return true;
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+ }
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}
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- return code;
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+ return false;
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}
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static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
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{
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- int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
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- int timing_vsync = 0, timing_hsync = 0;
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- struct hdmi_video_timings temp;
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+ int i;
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struct hdmi_cm cm = {-1};
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DSSDBG("hdmi_get_code\n");
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- for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
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- temp = cea_vesa_timings[i].timings;
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- if ((temp.pixel_clock == timing->pixel_clock) &&
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- (temp.x_res == timing->x_res) &&
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- (temp.y_res == timing->y_res)) {
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-
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- temp_hsync = temp.hfp + temp.hsw + temp.hbp;
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- timing_hsync = timing->hfp + timing->hsw + timing->hbp;
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- temp_vsync = temp.vfp + temp.vsw + temp.vbp;
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- timing_vsync = timing->vfp + timing->vsw + timing->vbp;
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-
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- DSSDBG("temp_hsync = %d , temp_vsync = %d"
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- "timing_hsync = %d, timing_vsync = %d\n",
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- temp_hsync, temp_hsync,
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- timing_hsync, timing_vsync);
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-
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- if ((temp_hsync == timing_hsync) &&
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- (temp_vsync == timing_vsync)) {
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- code = i;
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- cm.code = code_index[i];
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- if (code < 14)
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- cm.mode = HDMI_HDMI;
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- else
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- cm.mode = HDMI_DVI;
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- DSSDBG("Hdmi_code = %d mode = %d\n",
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- cm.code, cm.mode);
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- break;
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- }
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+ for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
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+ if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
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+ cm = cea_timings[i].cm;
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+ goto end;
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+ }
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+ }
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+ for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
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+ if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
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+ cm = vesa_timings[i].cm;
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+ goto end;
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}
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}
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- return cm;
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-}
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+end: return cm;
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-static void update_hdmi_timings(struct hdmi_config *cfg,
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- struct omap_video_timings *timings, int code)
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-{
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- cfg->timings.x_res = timings->x_res;
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- cfg->timings.y_res = timings->y_res;
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- cfg->timings.hbp = timings->hbp;
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- cfg->timings.hfp = timings->hfp;
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- cfg->timings.hsw = timings->hsw;
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- cfg->timings.vbp = timings->vbp;
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- cfg->timings.vfp = timings->vfp;
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- cfg->timings.vsw = timings->vsw;
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- cfg->timings.pixel_clock = timings->pixel_clock;
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- cfg->timings.vsync_pol = cea_vesa_timings[code].timings.vsync_pol;
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- cfg->timings.hsync_pol = cea_vesa_timings[code].timings.hsync_pol;
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}
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unsigned long hdmi_get_pixel_clock(void)
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@@ -325,7 +293,8 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
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static int hdmi_power_on(struct omap_dss_device *dssdev)
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{
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- int r, code = 0;
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+ int r;
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+ const struct hdmi_config *timing;
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struct omap_video_timings *p;
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unsigned long phy;
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@@ -341,9 +310,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev)
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dssdev->panel.timings.x_res,
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dssdev->panel.timings.y_res);
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- code = get_timings_index();
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- update_hdmi_timings(&hdmi.ip_data.cfg, p, code);
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-
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+ timing = hdmi_get_timings();
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+ if (timing == NULL) {
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+ /* HDMI code 4 corresponds to 640 * 480 VGA */
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+ hdmi.code = 4;
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+ /* DVI mode 1 corresponds to HDMI 0 to DVI */
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+ hdmi.mode = HDMI_DVI;
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+ hdmi.ip_data.cfg = vesa_timings[0];
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+ } else {
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+ hdmi.ip_data.cfg = *timing;
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+ }
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phy = p->pixel_clock;
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hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
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