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@@ -100,6 +100,44 @@ evo_kick(u32 *push, struct drm_device *dev, int id)
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/******************************************************************************
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* IRQ
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*****************************************************************************/
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+static void
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+nvd0_display_intr(struct drm_device *dev)
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+{
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+ u32 intr = nv_rd32(dev, 0x610088);
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+
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+ if (intr & 0x00000002) {
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+ u32 stat = nv_rd32(dev, 0x61009c);
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+ int chid = ffs(stat) - 1;
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+ if (chid >= 0) {
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+ u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
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+ u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
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+ u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
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+
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+ NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
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+ "0x%08x 0x%08x\n",
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+ chid, (mthd & 0x0000ffc), data, mthd, unkn);
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+ nv_wr32(dev, 0x61009c, (1 << chid));
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+ nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
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+ }
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+
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+ intr &= ~0x00000002;
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+ }
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+
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+ if (intr & 0x01000000) {
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+ u32 stat = nv_rd32(dev, 0x6100bc);
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+ nv_wr32(dev, 0x6100bc, stat);
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+ intr &= ~0x01000000;
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+ }
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+
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+ if (intr & 0x02000000) {
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+ u32 stat = nv_rd32(dev, 0x6108bc);
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+ nv_wr32(dev, 0x6108bc, stat);
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+ intr &= ~0x02000000;
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+ }
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+
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+ if (intr)
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+ NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
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+}
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/******************************************************************************
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* Init
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@@ -190,6 +228,7 @@ nvd0_display_destroy(struct drm_device *dev)
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pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
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nouveau_gpuobj_ref(NULL, &disp->mem);
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+ nouveau_irq_unregister(dev, 26);
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dev_priv->engine.display.priv = NULL;
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kfree(disp);
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@@ -208,6 +247,9 @@ nvd0_display_create(struct drm_device *dev)
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return -ENOMEM;
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dev_priv->engine.display.priv = disp;
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+ /* setup interrupt handling */
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+ nouveau_irq_register(dev, 26, nvd0_display_intr);
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+
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/* hash table and dma objects for the memory areas we care about */
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ret = nouveau_gpuobj_new(dev, NULL, 4 * 1024, 0x1000, 0, &disp->mem);
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if (ret)
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