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@@ -97,7 +97,7 @@ qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
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{
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{
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int count;
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int count;
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uint16_t word;
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uint16_t word;
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- uint32_t nv_cmd;
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+ uint32_t nv_cmd, wait_cnt;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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@@ -127,7 +127,13 @@ qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
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/* Wait for NVRAM to become ready */
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/* Wait for NVRAM to become ready */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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+ wait_cnt = NVR_WAIT_CNT;
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do {
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do {
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+ if (!--wait_cnt) {
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+ DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
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+ __func__, ha->host_no));
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+ break;
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+ }
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NVRAM_DELAY();
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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} while ((word & NVR_DATA_IN) == 0);
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@@ -301,16 +307,17 @@ qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
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{
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{
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int ret, stat;
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int ret, stat;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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- uint32_t word;
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+ uint32_t word, wait_cnt;
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uint16_t wprot, wprot_old;
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uint16_t wprot, wprot_old;
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/* Clear NVRAM write protection. */
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/* Clear NVRAM write protection. */
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ret = QLA_FUNCTION_FAILED;
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ret = QLA_FUNCTION_FAILED;
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- wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
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- stat = qla2x00_write_nvram_word_tmo(ha, 0,
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+
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+ wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
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+ stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
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__constant_cpu_to_le16(0x1234), 100000);
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__constant_cpu_to_le16(0x1234), 100000);
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- wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
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- if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
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+ wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
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+ if (stat != QLA_SUCCESS || wprot != 0x1234) {
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/* Write enable. */
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/* Write enable. */
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, NVR_DATA_OUT);
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qla2x00_nv_write(ha, 0);
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qla2x00_nv_write(ha, 0);
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@@ -341,14 +348,22 @@ qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
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/* Wait for NVRAM to become ready. */
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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+ wait_cnt = NVR_WAIT_CNT;
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do {
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do {
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+ if (!--wait_cnt) {
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+ DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
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+ "ready...\n", __func__,
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+ ha->host_no));
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+ break;
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+ }
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NVRAM_DELAY();
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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} while ((word & NVR_DATA_IN) == 0);
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- ret = QLA_SUCCESS;
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+ if (wait_cnt)
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+ ret = QLA_SUCCESS;
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} else
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} else
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- qla2x00_write_nvram_word(ha, 0, wprot_old);
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+ qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
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return ret;
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return ret;
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}
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}
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@@ -357,7 +372,7 @@ static void
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qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
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qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
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{
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{
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
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- uint32_t word;
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+ uint32_t word, wait_cnt;
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if (stat != QLA_SUCCESS)
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if (stat != QLA_SUCCESS)
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return;
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return;
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@@ -393,7 +408,13 @@ qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
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/* Wait for NVRAM to become ready. */
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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+ wait_cnt = NVR_WAIT_CNT;
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do {
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do {
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+ if (!--wait_cnt) {
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+ DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
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+ __func__, ha->host_no));
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+ break;
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+ }
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NVRAM_DELAY();
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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word = RD_REG_WORD(®->nvram);
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} while ((word & NVR_DATA_IN) == 0);
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} while ((word & NVR_DATA_IN) == 0);
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@@ -500,6 +521,20 @@ qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
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ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
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ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
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*man_id = LSB(ids);
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*man_id = LSB(ids);
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*flash_id = MSB(ids);
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*flash_id = MSB(ids);
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+
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+ /* Check if man_id and flash_id are valid. */
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+ if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
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+ /* Read information using 0x9f opcode
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+ * Device ID, Mfg ID would be read in the format:
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+ * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
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+ * Example: ATMEL 0x00 01 45 1F
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+ * Extract MFG and Dev ID from last two bytes.
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+ */
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+ ids = qla24xx_read_flash_dword(ha,
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+ flash_data_to_access_addr(0xd009f));
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+ *man_id = LSB(ids);
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+ *flash_id = MSB(ids);
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+ }
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}
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}
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int
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int
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@@ -508,8 +543,8 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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{
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{
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int ret;
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int ret;
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uint32_t liter;
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uint32_t liter;
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- uint32_t sec_mask, rest_addr, conf_addr;
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- uint32_t fdata;
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+ uint32_t sec_mask, rest_addr, conf_addr, sec_end_mask;
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+ uint32_t fdata, findex ;
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uint8_t man_id, flash_id;
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uint8_t man_id, flash_id;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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@@ -519,6 +554,7 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
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DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
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ha->host_no, man_id, flash_id));
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ha->host_no, man_id, flash_id));
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+ sec_end_mask = 0;
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conf_addr = flash_conf_to_access_addr(0x03d8);
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conf_addr = flash_conf_to_access_addr(0x03d8);
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switch (man_id) {
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switch (man_id) {
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case 0xbf: /* STT flash. */
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case 0xbf: /* STT flash. */
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@@ -531,6 +567,12 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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rest_addr = 0x3fff;
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rest_addr = 0x3fff;
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sec_mask = 0x3c000;
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sec_mask = 0x3c000;
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break;
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break;
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+ case 0x1f: // Atmel 26DF081A
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+ rest_addr = 0x0fff;
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+ sec_mask = 0xff000;
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+ sec_end_mask = 0x003ff;
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+ conf_addr = flash_conf_to_access_addr(0x0320);
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+ break;
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default:
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default:
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/* Default to 64 kb sector size. */
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/* Default to 64 kb sector size. */
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rest_addr = 0x3fff;
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rest_addr = 0x3fff;
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@@ -545,11 +587,30 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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/* Disable flash write-protection. */
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/* Disable flash write-protection. */
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qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
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qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
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+ /* Some flash parts need an additional zero-write to clear bits.*/
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+ qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
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do { /* Loop once to provide quick error exit. */
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do { /* Loop once to provide quick error exit. */
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for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
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for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
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+ if (man_id == 0x1f) {
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+ findex = faddr << 2;
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+ fdata = findex & sec_mask;
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+ } else {
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+ findex = faddr;
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+ fdata = (findex & sec_mask) << 2;
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+ }
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+
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/* Are we at the beginning of a sector? */
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/* Are we at the beginning of a sector? */
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- if ((faddr & rest_addr) == 0) {
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+ if ((findex & rest_addr) == 0) {
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+ /*
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+ * Do sector unprotect at 4K boundry for Atmel
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+ * part.
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+ */
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+ if (man_id == 0x1f)
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+ qla24xx_write_flash_dword(ha,
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+ flash_conf_to_access_addr(0x0339),
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+ (fdata & 0xff00) | ((fdata << 16) &
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+ 0xff0000) | ((fdata >> 16) & 0xff));
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fdata = (faddr & sec_mask) << 2;
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fdata = (faddr & sec_mask) << 2;
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ret = qla24xx_write_flash_dword(ha, conf_addr,
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ret = qla24xx_write_flash_dword(ha, conf_addr,
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(fdata & 0xff00) |((fdata << 16) &
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(fdata & 0xff00) |((fdata << 16) &
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@@ -570,6 +631,14 @@ qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
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ha->host_no, faddr, *dwptr));
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ha->host_no, faddr, *dwptr));
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break;
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break;
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}
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}
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+
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+ /* Do sector protect at 4K boundry for Atmel part. */
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+ if (man_id == 0x1f &&
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+ ((faddr & sec_end_mask) == 0x3ff))
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+ qla24xx_write_flash_dword(ha,
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+ flash_conf_to_access_addr(0x0336),
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+ (fdata & 0xff00) | ((fdata << 16) &
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+ 0xff0000) | ((fdata >> 16) & 0xff));
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}
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}
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} while (0);
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} while (0);
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