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@@ -175,7 +175,7 @@ ENTRY(_sleep_mode)
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call _set_sic_iwr;
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R0 = 0xFFFF (Z);
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- call _set_rtc_istat
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+ call _set_rtc_istat;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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@@ -213,7 +213,7 @@ ENTRY(_hibernate_mode)
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call _set_sic_iwr;
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R0 = 0xFFFF (Z);
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- call _set_rtc_istat
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+ call _set_rtc_istat;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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@@ -288,23 +288,22 @@ ENTRY(_sleep_deeper)
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P3 = R0;
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R0 = IWR_ENABLE(0);
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call _set_sic_iwr;
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- call _set_dram_srfs;
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+ call _set_dram_srfs; /* Set SDRAM Self Refresh */
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/* Clear all the interrupts,bits sticky */
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R0 = 0xFFFF (Z);
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- call _set_rtc_istat
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-
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+ call _set_rtc_istat;
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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R6 = W[P0](z);
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R0.L = 0xF;
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- W[P0] = R0.l;
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+ W[P0] = R0.l; /* Set Max VCO to SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R5 = W[P0](z);
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R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
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- W[P0] = R0.l;
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+ W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
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SSYNC;
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IDLE;
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@@ -320,29 +319,28 @@ ENTRY(_sleep_deeper)
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R1 = R1|R2;
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R2 = DEPOSIT(R7, R1);
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- W[P0] = R2;
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+ W[P0] = R2; /* Set Min Core Voltage */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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+ R0 = P3;
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+ call _set_sic_iwr; /* Set Awake from IDLE */
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+
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = W[P0](z);
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BITSET (R0, 3);
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- W[P0] = R0.L;
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-
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- R0 = P3;
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- call _set_sic_iwr;
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-
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+ W[P0] = R0.L; /* Turn CCLK OFF */
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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- call _set_sic_iwr;
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+ call _set_sic_iwr; /* Set Awake from IDLE PLL */
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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@@ -355,15 +353,15 @@ ENTRY(_sleep_deeper)
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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- W[P0]= R6;
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+ W[P0]= R6; /* Restore CCLK and SCLK divider */
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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- w[p0] = R5;
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+ w[p0] = R5; /* Restore VCO multiplier */
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IDLE;
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call _test_pll_locked;
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- call _unset_dram_srfs;
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+ call _unset_dram_srfs; /* SDRAM Self Refresh Off */
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STI R4;
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