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@@ -817,23 +817,12 @@ void __init ep93xx_register_i2s(void)
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#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
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EP93XX_SYSCON_I2SCLKDIV_SPOL)
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-int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
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+int ep93xx_i2s_acquire(void)
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{
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unsigned val;
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- /* Sanity check */
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- if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK)
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- return -EINVAL;
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- if (i2s_config & ~EP93XX_I2SCLKDIV_MASK)
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- return -EINVAL;
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-
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- /* Must have only one of I2SONSSP/I2SONAC97 set */
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- if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) ==
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- (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97))
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- return -EINVAL;
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-
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- ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
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- ep93xx_devcfg_set_bits(i2s_pins);
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+ ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
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+ EP93XX_SYSCON_DEVCFG_I2S_MASK);
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/*
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* This is potentially racy with the clock api for i2s_mclk, sclk and
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@@ -843,7 +832,7 @@ int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
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*/
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val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
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val &= ~EP93XX_I2SCLKDIV_MASK;
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- val |= i2s_config;
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+ val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
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ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
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return 0;
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