|
@@ -562,6 +562,12 @@ static const struct snd_kcontrol_new twl4030_snd_controls[] = {
|
|
|
SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
|
|
|
TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
|
|
|
3, 0x12, 1, analog_tlv),
|
|
|
+ SOC_DOUBLE_R("DAC1 Analog Playback Switch",
|
|
|
+ TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
|
|
|
+ 1, 1, 0),
|
|
|
+ SOC_DOUBLE_R("DAC2 Analog Playback Switch",
|
|
|
+ TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
|
|
|
+ 1, 1, 0),
|
|
|
|
|
|
/* Separate output gain controls */
|
|
|
SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
|
|
@@ -626,14 +632,29 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
|
|
|
SND_SOC_DAPM_DAC("DACL2", "Left Rear Playback",
|
|
|
TWL4030_REG_AVDAC_CTL, 3, 0),
|
|
|
|
|
|
+ /* Analog PGAs */
|
|
|
+ SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
|
|
|
+ 0, 0, NULL, 0),
|
|
|
+ SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
|
|
|
+ 0, 0, NULL, 0),
|
|
|
+ SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
|
|
|
+ 0, 0, NULL, 0),
|
|
|
+ SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
|
|
|
+ 0, 0, NULL, 0),
|
|
|
+
|
|
|
SND_SOC_DAPM_ADC("ADCL", "Left Capture", SND_SOC_NOPM, 0, 0),
|
|
|
SND_SOC_DAPM_ADC("ADCR", "Right Capture", SND_SOC_NOPM, 0, 0),
|
|
|
};
|
|
|
|
|
|
static const struct snd_soc_dapm_route intercon[] = {
|
|
|
+ {"ARXL1_APGA", NULL, "DACL1"},
|
|
|
+ {"ARXR1_APGA", NULL, "DACR1"},
|
|
|
+ {"ARXL2_APGA", NULL, "DACL2"},
|
|
|
+ {"ARXR2_APGA", NULL, "DACR2"},
|
|
|
+
|
|
|
/* outputs */
|
|
|
- {"OUTL", NULL, "DACL2"},
|
|
|
- {"OUTR", NULL, "DACR2"},
|
|
|
+ {"OUTL", NULL, "ARXL2_APGA"},
|
|
|
+ {"OUTR", NULL, "ARXR2_APGA"},
|
|
|
|
|
|
/* inputs */
|
|
|
{"ADCL", NULL, "INL"},
|