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@@ -33,6 +33,8 @@
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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+#include <linux/of.h>
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+
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mpc8260.h>
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@@ -45,13 +47,12 @@
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#include <sysdev/fsl_soc.h>
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static void cpm2_dpinit(void);
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-cpm_cpm2_t *cpmp; /* Pointer to comm processor space */
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+cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
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/* We allocate this here because it is used almost exclusively for
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* the communication processor devices.
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*/
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-cpm2_map_t *cpm2_immr;
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-intctl_cpm2_t *cpm2_intctl;
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+cpm2_map_t __iomem *cpm2_immr;
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#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
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of space for CPM as it is larger
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@@ -60,8 +61,11 @@ intctl_cpm2_t *cpm2_intctl;
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void
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cpm2_reset(void)
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{
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- cpm2_immr = (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
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- cpm2_intctl = cpm2_map(im_intctl);
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+#ifdef CONFIG_PPC_85xx
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+ cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
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+#else
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+ cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
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+#endif
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/* Reclaim the DP memory for our use.
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*/
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@@ -91,7 +95,7 @@ cpm2_reset(void)
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void
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cpm_setbrg(uint brg, uint rate)
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{
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- volatile uint *bp;
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+ u32 __iomem *bp;
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/* This is good enough to get SMCs running.....
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*/
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@@ -113,7 +117,8 @@ cpm_setbrg(uint brg, uint rate)
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void
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cpm2_fastbrg(uint brg, uint rate, int div16)
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{
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- volatile uint *bp;
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+ u32 __iomem *bp;
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+ u32 val;
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if (brg < 4) {
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bp = cpm2_map_size(im_brgc1, 16);
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@@ -123,10 +128,11 @@ cpm2_fastbrg(uint brg, uint rate, int div16)
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brg -= 4;
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}
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bp += brg;
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- *bp = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
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+ val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
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if (div16)
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- *bp |= CPM_BRG_DIV16;
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+ val |= CPM_BRG_DIV16;
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+ out_be32(bp, val);
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cpm2_unmap(bp);
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}
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@@ -135,8 +141,8 @@ int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
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int ret = 0;
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int shift;
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int i, bits = 0;
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- cpmux_t *im_cpmux;
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- u32 *reg;
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+ cpmux_t __iomem *im_cpmux;
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+ u32 __iomem *reg;
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u32 mask = 7;
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u8 clk_map [24][3] = {
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{CPM_CLK_FCC1, CPM_BRG5, 0},
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@@ -228,13 +234,33 @@ static spinlock_t cpm_dpmem_lock;
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* until the memory subsystem goes up... */
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static rh_block_t cpm_boot_dpmem_rh_block[16];
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static rh_info_t cpm_dpmem_info;
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-static u8* im_dprambase;
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+static u8 __iomem *im_dprambase;
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static void cpm2_dpinit(void)
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{
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- spin_lock_init(&cpm_dpmem_lock);
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+ struct resource r;
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+
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+#ifdef CONFIG_PPC_CPM_NEW_BINDING
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+ struct device_node *np;
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+
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+ np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
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+ if (!np)
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+ panic("Cannot find CPM2 node");
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- im_dprambase = ioremap(CPM_MAP_ADDR, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
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+ if (of_address_to_resource(np, 1, &r))
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+ panic("Cannot get CPM2 resource 1");
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+
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+ of_node_put(np);
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+#else
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+ r.start = CPM_MAP_ADDR;
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+ r.end = r.start + CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE - 1;
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+#endif
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+
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+ im_dprambase = ioremap(r.start, r.end - r.start + 1);
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+ if (!im_dprambase)
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+ panic("Cannot map DPRAM");
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+
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+ spin_lock_init(&cpm_dpmem_lock);
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/* initialize the info header */
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rh_init(&cpm_dpmem_info, 1,
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@@ -248,7 +274,7 @@ static void cpm2_dpinit(void)
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* varies with the processor and the microcode patches activated.
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* But the following should be at least safe.
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*/
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- rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
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+ rh_attach_region(&cpm_dpmem_info, 0, r.end - r.start + 1);
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}
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/* This function returns an index into the DPRAM area.
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