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@@ -205,8 +205,8 @@
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#define S3C6400_CLKSRC_MMC2_SHIFT (22)
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#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20)
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#define S3C6400_CLKSRC_MMC1_SHIFT (20)
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-#define S3C6400_CLKSRC_MMC0_MASK (0xf << 1)
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-#define S3C6400_CLKSRC_MMC0_SHIFT (1)
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+#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18)
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+#define S3C6400_CLKSRC_MMC0_SHIFT (18)
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#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16)
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#define S3C6400_CLKSRC_SPI1_SHIFT (16)
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#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14)
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