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@@ -69,6 +69,9 @@ module_param(emulate_invalid_guest_state, bool, S_IRUGO);
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static int __read_mostly vmm_exclusive = 1;
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module_param(vmm_exclusive, bool, S_IRUGO);
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+static int __read_mostly yield_on_hlt = 1;
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+module_param(yield_on_hlt, bool, S_IRUGO);
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+
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#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
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(X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
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#define KVM_GUEST_CR0_MASK \
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@@ -1009,6 +1012,17 @@ static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
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vmx_set_interrupt_shadow(vcpu, 0);
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}
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+static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
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+{
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+ /* Ensure that we clear the HLT state in the VMCS. We don't need to
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+ * explicitly skip the instruction because if the HLT state is set, then
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+ * the instruction is already executing and RIP has already been
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+ * advanced. */
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+ if (!yield_on_hlt &&
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+ vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
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+ vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
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+}
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+
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static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
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bool has_error_code, u32 error_code,
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bool reinject)
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@@ -1035,6 +1049,7 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
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intr_info |= INTR_TYPE_HARD_EXCEPTION;
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vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
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+ vmx_clear_hlt(vcpu);
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}
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static bool vmx_rdtscp_supported(void)
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@@ -1419,7 +1434,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
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&_pin_based_exec_control) < 0)
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return -EIO;
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- min = CPU_BASED_HLT_EXITING |
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+ min =
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#ifdef CONFIG_X86_64
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CPU_BASED_CR8_LOAD_EXITING |
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CPU_BASED_CR8_STORE_EXITING |
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@@ -1432,6 +1447,10 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
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CPU_BASED_MWAIT_EXITING |
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CPU_BASED_MONITOR_EXITING |
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CPU_BASED_INVLPG_EXITING;
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+
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+ if (yield_on_hlt)
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+ min |= CPU_BASED_HLT_EXITING;
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+
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opt = CPU_BASED_TPR_SHADOW |
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CPU_BASED_USE_MSR_BITMAPS |
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CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
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@@ -2728,7 +2747,7 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
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vmcs_writel(GUEST_IDTR_BASE, 0);
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vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
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- vmcs_write32(GUEST_ACTIVITY_STATE, 0);
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+ vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
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vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
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vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
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@@ -2821,6 +2840,7 @@ static void vmx_inject_irq(struct kvm_vcpu *vcpu)
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} else
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intr |= INTR_TYPE_EXT_INTR;
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vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
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+ vmx_clear_hlt(vcpu);
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}
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static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
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@@ -2848,6 +2868,7 @@ static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
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}
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vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
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INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
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+ vmx_clear_hlt(vcpu);
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}
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static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
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