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@@ -12,19 +12,19 @@
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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- *
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+ *
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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- *
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+ *
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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* Or, point your browser to http://www.gnu.org/copyleft/gpl.html
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- *
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+ *
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*/
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#include <linux/module.h>
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@@ -58,7 +58,7 @@ module_param_named(verbose, bt878_verbose, int, 0444);
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MODULE_PARM_DESC(verbose,
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"verbose startup messages, default is 1 (yes)");
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module_param_named(debug, bt878_debug, int, 0644);
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-MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
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+MODULE_PARM_DESC(debug, "Turn on/off debugging, default is 0 (off).");
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int bt878_num;
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struct bt878 bt878[BT878_MAX];
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@@ -128,21 +128,21 @@ static int bt878_mem_alloc(struct bt878 *bt)
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}
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/* RISC instructions */
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-#define RISC_WRITE (0x01 << 28)
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-#define RISC_JUMP (0x07 << 28)
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-#define RISC_SYNC (0x08 << 28)
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+#define RISC_WRITE (0x01 << 28)
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+#define RISC_JUMP (0x07 << 28)
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+#define RISC_SYNC (0x08 << 28)
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/* RISC bits */
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-#define RISC_WR_SOL (1 << 27)
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-#define RISC_WR_EOL (1 << 26)
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-#define RISC_IRQ (1 << 24)
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+#define RISC_WR_SOL (1 << 27)
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+#define RISC_WR_EOL (1 << 26)
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+#define RISC_IRQ (1 << 24)
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#define RISC_STATUS(status) ((((~status) & 0x0F) << 20) | ((status & 0x0F) << 16))
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-#define RISC_SYNC_RESYNC (1 << 15)
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-#define RISC_SYNC_FM1 0x06
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-#define RISC_SYNC_VRO 0x0C
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+#define RISC_SYNC_RESYNC (1 << 15)
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+#define RISC_SYNC_FM1 0x06
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+#define RISC_SYNC_VRO 0x0C
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#define RISC_FLUSH() bt->risc_pos = 0
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-#define RISC_INSTR(instr) bt->risc_cpu[bt->risc_pos++] = cpu_to_le32(instr)
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+#define RISC_INSTR(instr) bt->risc_cpu[bt->risc_pos++] = cpu_to_le32(instr)
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static int bt878_make_risc(struct bt878 *bt)
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{
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@@ -173,7 +173,7 @@ static void bt878_risc_program(struct bt878 *bt, u32 op_sync_orin)
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RISC_INSTR(RISC_SYNC | RISC_SYNC_FM1 | op_sync_orin);
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RISC_INSTR(0);
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- dprintk("bt878: risc len lines %u, bytes per line %u\n",
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+ dprintk("bt878: risc len lines %u, bytes per line %u\n",
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bt->line_count, bt->line_bytes);
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for (line = 0; line < bt->line_count; line++) {
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// At the beginning of every block we issue an IRQ with previous (finished) block number set
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@@ -228,14 +228,14 @@ void bt878_start(struct bt878 *bt, u32 controlreg, u32 op_sync_orin,
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* Hacked for DST to:
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* SCERR | OCERR | FDSR | FTRGT | FBUS | RISCI
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*/
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- int_mask = BT878_ASCERR | BT878_AOCERR | BT878_APABORT |
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- BT878_ARIPERR | BT878_APPERR | BT878_AFDSR | BT878_AFTRGT |
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+ int_mask = BT878_ASCERR | BT878_AOCERR | BT878_APABORT |
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+ BT878_ARIPERR | BT878_APPERR | BT878_AFDSR | BT878_AFTRGT |
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BT878_AFBUS | BT878_ARISCI;
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/* ignore pesky bits */
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int_mask &= ~irq_err_ignore;
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-
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+
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btwrite(int_mask, BT878_AINT_MASK);
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btwrite(controlreg, BT878_AGPIO_DMA_CTL);
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}
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