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@@ -142,8 +142,8 @@
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#define DRV_MODULE_NAME "cassini"
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#define PFX DRV_MODULE_NAME ": "
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-#define DRV_MODULE_VERSION "1.4"
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-#define DRV_MODULE_RELDATE "1 July 2004"
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+#define DRV_MODULE_VERSION "1.5"
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+#define DRV_MODULE_RELDATE "4 Jan 2008"
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#define CAS_DEF_MSG_ENABLE \
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(NETIF_MSG_DRV | \
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@@ -336,30 +336,6 @@ static inline void cas_mask_intr(struct cas *cp)
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cas_disable_irq(cp, i);
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}
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-static inline void cas_buffer_init(cas_page_t *cp)
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-{
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- struct page *page = cp->buffer;
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- atomic_set((atomic_t *)&page->lru.next, 1);
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-}
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-
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-static inline int cas_buffer_count(cas_page_t *cp)
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-{
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- struct page *page = cp->buffer;
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- return atomic_read((atomic_t *)&page->lru.next);
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-}
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-
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-static inline void cas_buffer_inc(cas_page_t *cp)
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-{
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- struct page *page = cp->buffer;
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- atomic_inc((atomic_t *)&page->lru.next);
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-}
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-
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-static inline void cas_buffer_dec(cas_page_t *cp)
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-{
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- struct page *page = cp->buffer;
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- atomic_dec((atomic_t *)&page->lru.next);
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-}
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-
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static void cas_enable_irq(struct cas *cp, const int ring)
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{
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if (ring == 0) { /* all but TX_DONE */
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@@ -497,7 +473,6 @@ static int cas_page_free(struct cas *cp, cas_page_t *page)
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{
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pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
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PCI_DMA_FROMDEVICE);
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- cas_buffer_dec(page);
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__free_pages(page->buffer, cp->page_order);
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kfree(page);
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return 0;
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@@ -527,7 +502,6 @@ static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
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page->buffer = alloc_pages(flags, cp->page_order);
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if (!page->buffer)
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goto page_err;
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- cas_buffer_init(page);
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page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
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cp->page_size, PCI_DMA_FROMDEVICE);
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return page;
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@@ -606,7 +580,7 @@ static void cas_spare_recover(struct cas *cp, const gfp_t flags)
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list_for_each_safe(elem, tmp, &list) {
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cas_page_t *page = list_entry(elem, cas_page_t, list);
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- if (cas_buffer_count(page) > 1)
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+ if (page_count(page->buffer) > 1)
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continue;
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list_del(elem);
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@@ -1374,7 +1348,7 @@ static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
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cas_page_t *page = cp->rx_pages[1][index];
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cas_page_t *new;
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- if (cas_buffer_count(page) == 1)
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+ if (page_count(page->buffer) == 1)
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return page;
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new = cas_page_dequeue(cp);
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@@ -1394,7 +1368,7 @@ static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
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cas_page_t **page1 = cp->rx_pages[1];
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/* swap if buffer is in use */
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- if (cas_buffer_count(page0[index]) > 1) {
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+ if (page_count(page0[index]->buffer) > 1) {
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cas_page_t *new = cas_page_spare(cp, index);
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if (new) {
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page1[index] = page0[index];
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@@ -1979,6 +1953,7 @@ static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
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struct cas_page *page;
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struct sk_buff *skb;
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void *addr, *crcaddr;
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+ __sum16 csum;
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char *p;
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hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
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@@ -2062,10 +2037,10 @@ static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
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skb_shinfo(skb)->nr_frags++;
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skb->data_len += hlen - swivel;
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+ skb->truesize += hlen - swivel;
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skb->len += hlen - swivel;
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get_page(page->buffer);
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- cas_buffer_inc(page);
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frag->page = page->buffer;
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frag->page_offset = off;
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frag->size = hlen - swivel;
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@@ -2090,7 +2065,6 @@ static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
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frag++;
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get_page(page->buffer);
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- cas_buffer_inc(page);
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frag->page = page->buffer;
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frag->page_offset = 0;
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frag->size = hlen;
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@@ -2158,14 +2132,15 @@ end_copy_pkt:
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skb_put(skb, alloclen);
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}
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- i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
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+ csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3]));
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if (cp->crc_size) {
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/* checksum includes FCS. strip it out. */
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- i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
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+ csum = csum_fold(csum_partial(crcaddr, cp->crc_size,
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+ csum_unfold(csum)));
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if (addr)
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cas_page_unmap(addr);
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}
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- skb->csum = ntohs(i ^ 0xffff);
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+ skb->csum = csum_unfold(~csum);
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skb->ip_summed = CHECKSUM_COMPLETE;
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skb->protocol = eth_type_trans(skb, cp->dev);
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return len;
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@@ -2253,7 +2228,7 @@ static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
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released = 0;
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while (entry != last) {
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/* make a new buffer if it's still in use */
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- if (cas_buffer_count(page[entry]) > 1) {
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+ if (page_count(page[entry]->buffer) > 1) {
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cas_page_t *new = cas_page_dequeue(cp);
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if (!new) {
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/* let the timer know that we need to
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@@ -2611,7 +2586,7 @@ static int cas_poll(struct napi_struct *napi, int budget)
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{
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struct cas *cp = container_of(napi, struct cas, napi);
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struct net_device *dev = cp->dev;
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- int i, enable_intr, todo, credits;
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+ int i, enable_intr, credits;
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u32 status = readl(cp->regs + REG_INTR_STATUS);
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unsigned long flags;
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@@ -4375,7 +4350,7 @@ static int cas_close(struct net_device *dev)
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struct cas *cp = netdev_priv(dev);
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#ifdef USE_NAPI
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- napi_enable(&cp->napi);
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+ napi_disable(&cp->napi);
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#endif
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/* Make sure we don't get distracted by suspend/resume */
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mutex_lock(&cp->pm_mutex);
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@@ -4872,6 +4847,90 @@ static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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return rc;
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}
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+/* When this chip sits underneath an Intel 31154 bridge, it is the
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+ * only subordinate device and we can tweak the bridge settings to
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+ * reflect that fact.
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+ */
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+static void __devinit cas_program_bridge(struct pci_dev *cas_pdev)
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+{
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+ struct pci_dev *pdev = cas_pdev->bus->self;
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+ u32 val;
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+
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+ if (!pdev)
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+ return;
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+
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+ if (pdev->vendor != 0x8086 || pdev->device != 0x537c)
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+ return;
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+
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+ /* Clear bit 10 (Bus Parking Control) in the Secondary
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+ * Arbiter Control/Status Register which lives at offset
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+ * 0x41. Using a 32-bit word read/modify/write at 0x40
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+ * is much simpler so that's how we do this.
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+ */
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+ pci_read_config_dword(pdev, 0x40, &val);
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+ val &= ~0x00040000;
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+ pci_write_config_dword(pdev, 0x40, val);
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+
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+ /* Max out the Multi-Transaction Timer settings since
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+ * Cassini is the only device present.
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+ *
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+ * The register is 16-bit and lives at 0x50. When the
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+ * settings are enabled, it extends the GRANT# signal
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+ * for a requestor after a transaction is complete. This
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+ * allows the next request to run without first needing
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+ * to negotiate the GRANT# signal back.
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+ *
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+ * Bits 12:10 define the grant duration:
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+ *
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+ * 1 -- 16 clocks
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+ * 2 -- 32 clocks
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+ * 3 -- 64 clocks
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+ * 4 -- 128 clocks
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+ * 5 -- 256 clocks
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+ *
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+ * All other values are illegal.
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+ *
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+ * Bits 09:00 define which REQ/GNT signal pairs get the
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+ * GRANT# signal treatment. We set them all.
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+ */
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+ pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
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+
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+ /* The Read Prefecth Policy register is 16-bit and sits at
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+ * offset 0x52. It enables a "smart" pre-fetch policy. We
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+ * enable it and max out all of the settings since only one
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+ * device is sitting underneath and thus bandwidth sharing is
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+ * not an issue.
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+ *
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+ * The register has several 3 bit fields, which indicates a
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+ * multiplier applied to the base amount of prefetching the
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+ * chip would do. These fields are at:
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+ *
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+ * 15:13 --- ReRead Primary Bus
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+ * 12:10 --- FirstRead Primary Bus
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+ * 09:07 --- ReRead Secondary Bus
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+ * 06:04 --- FirstRead Secondary Bus
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+ *
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+ * Bits 03:00 control which REQ/GNT pairs the prefetch settings
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+ * get enabled on. Bit 3 is a grouped enabler which controls
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+ * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control
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+ * the individual REQ/GNT pairs [2:0].
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+ */
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+ pci_write_config_word(pdev, 0x52,
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+ (0x7 << 13) |
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+ (0x7 << 10) |
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+ (0x7 << 7) |
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+ (0x7 << 4) |
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+ (0xf << 0));
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+
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+ /* Force cacheline size to 0x8 */
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+ pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
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+
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+ /* Force latency timer to maximum setting so Cassini can
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+ * sit on the bus as long as it likes.
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+ */
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+ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff);
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+}
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+
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static int __devinit cas_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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@@ -4927,6 +4986,8 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
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printk(KERN_WARNING PFX "Could not enable MWI for %s\n",
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pci_name(pdev));
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+ cas_program_bridge(pdev);
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+
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/*
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* On some architectures, the default cache line size set
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* by pci_try_set_mwi reduces perforamnce. We have to increase
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