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@@ -74,6 +74,28 @@ u8 cpu_mask;
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* OMAP2/3 specific clock functions
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* OMAP2/3 specific clock functions
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*-------------------------------------------------------------------------*/
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*-------------------------------------------------------------------------*/
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+/**
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+ * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
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+ * @clk: struct clk *
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+ *
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+ * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes
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+ * don't take effect until the VALID_CONFIG bit is written, write the
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+ * VALID_CONFIG bit and wait for the write to complete. No return value.
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+ */
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+static void _omap2xxx_clk_commit(struct clk *clk)
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+{
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+ if (!cpu_is_omap24xx())
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+ return;
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+
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+ if (!(clk->flags & DELAYED_APP))
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+ return;
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+
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+ prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
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+ OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
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+ /* OCP barrier */
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+ prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
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+}
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+
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/*
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/*
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* _dpll_test_fint - test whether an Fint value is valid for the DPLL
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* _dpll_test_fint - test whether an Fint value is valid for the DPLL
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* @clk: DPLL struct clk to test
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* @clk: DPLL struct clk to test
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@@ -685,11 +707,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
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clk->rate = clk->parent->rate / new_div;
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clk->rate = clk->parent->rate / new_div;
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- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
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- prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
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- OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
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- wmb();
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- }
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+ _omap2xxx_clk_commit(clk);
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return 0;
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return 0;
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}
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}
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@@ -772,10 +790,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
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__raw_writel(v, clk->clksel_reg);
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__raw_writel(v, clk->clksel_reg);
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wmb();
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wmb();
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- if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
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- __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
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- wmb();
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- }
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+ _omap2xxx_clk_commit(clk);
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if (clk->usecount > 0)
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if (clk->usecount > 0)
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_omap2_clk_enable(clk);
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_omap2_clk_enable(clk);
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