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@@ -217,7 +217,7 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
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return false;
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}
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-#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
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+#define INTELPllInvalid(s) do { DRM_DEBUG(s); return false; } while (0)
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/**
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* Returns whether the given set of divisors are valid for a given refclk with
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* the given connectors.
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@@ -726,7 +726,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
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int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
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int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
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- int refclk;
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+ int refclk, num_outputs = 0;
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intel_clock_t clock;
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u32 dpll = 0, fp = 0, dspcntr, pipeconf;
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bool ok, is_sdvo = false, is_dvo = false;
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@@ -763,9 +763,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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is_crt = true;
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break;
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}
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+
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+ num_outputs++;
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}
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- if (IS_I9XX(dev)) {
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+ if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
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+ refclk = dev_priv->lvds_ssc_freq * 1000;
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+ DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
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+ } else if (IS_I9XX(dev)) {
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refclk = 96000;
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} else {
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refclk = 48000;
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@@ -824,11 +829,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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- if (is_tv) {
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+ if (is_sdvo && is_tv)
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+ dpll |= PLL_REF_INPUT_TVCLKINBC;
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+ else if (is_tv)
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/* XXX: just matching BIOS for now */
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-/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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+ /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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- }
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+ else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
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+ dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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